Intelligent computation techniques for optimization of the shortest path in an asynchronous network-on-chip

Network-on-chip (NoC) offers itself to be a suitable interconnection structure and as a viable alternative for system-on-chip, and hence is employed in very-large-scale integration (VLSI) design. An asynchronous network-on-chip (ANoC) design has low energy consumption because of the absence of the clock. However, obtaining optimal path routing in an asynchronous network-on-chip poses computational complexities. In this work, the shortest optimal paths are determined by employing five contemporary optimization techniques, including the harmony search (HS) algorithm using the Hopfield neural network (HNN) in an ANoC mesh topology. Using optimal parameters, in an ANoC, the energy consumption is significantly reduced and a faster convergence speed is achieved. The HS technique was found to have the least consumption of energy and time-complexity in the investigated techniques. HS technique outperformed all the other techniques in various aspects, making it the most suitable for determining the optimal shortest path.