Automated least-significant bit datapath optimization for FPGAs
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[1] Vaughn Betz,et al. VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.
[2] Mark Stephenson,et al. Bidwidth analysis with application to silicon compilation , 2000, PLDI '00.
[3] Scott Hauck,et al. Precis: a design-time precision analysis tool , 2002, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.
[4] Y. C. Lim,et al. Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications , 1992, IEEE Trans. Computers.
[5] Alok N. Choudhary,et al. Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[6] Wayne Luk,et al. The Multiple Wordlength Paradigm , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).
[7] Seehyun Kim,et al. Fixed-point optimization utility for C and C++ based digital signal processing programs , 1998 .
[8] E. Swartzlander,et al. Truncated multiplication with correction constant [for DSP] , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.
[9] C. D. Gelatt,et al. Optimization by Simulated Annealing , 1983, Science.
[10] Michael J. Schulte,et al. FPGA Resource Reduction Through Truncated Multiplication , 2001, FPL.
[11] Wonyong Sung,et al. Simulation-based word-length optimization method for fixed-point digital signal processing systems , 1995, IEEE Trans. Signal Process..
[12] Mark William Stephenson,et al. Bitwise: Optimizing Bitwidths Using Data-Range Propagation , 2000 .