Digitale Hardware/Software-Systeme: Synthese und Optimierung, 2. Auflage

[1]  Alice C. Parker,et al.  A methodology and design tools to support system-level VLSI design , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Alice C. Parker,et al.  Synthesis of application-specific multiprocessor architectures , 1991, 28th ACM/IEEE Design Automation Conference.

[3]  Shapour Azarm,et al.  Multi-level Multi-objective Genetic Algorithm Using Entropy to Preserve Diversity , 2003, EMO.

[4]  Edward A. Lee,et al.  Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model , 1995, Proceedings of the Eighth International Symposium on System Synthesis.

[5]  Gary B. Lamont,et al.  Multiobjective evolutionary algorithms: classifications, analyses, and new innovations , 1999 .

[6]  Peter J. Fleming,et al.  Evolutionary many-objective optimisation: an exploratory analysis , 2003, The 2003 Congress on Evolutionary Computation, 2003. CEC '03..

[7]  Thomas Kailath,et al.  Regular iterative algorithms and their implementation on processor arrays , 1988, Proc. IEEE.

[8]  Jürgen Teich.  A compiler for application specific processor arrays , 1993 .

[9]  Rocquencourt,et al.  Analysis of Deadline Scheduled Real-Time Systems , 1996 .

[10]  Raymond Reiter,et al.  Scheduling Parallel Computations , 1968, J. ACM.

[11]  James F. Ready.  VRTX: A Real-Time Operating System for Embedded Microprocessor Applications , 1986, IEEE Micro.

[12]  Jürgen Teich,et al.  FunState-an internal design representation for codesign , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[13]  T. C. May,et al.  Instruction-set matching and selection for DSP and ASIP code generation , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[14]  Donald E. Thomas,et al.  Architectural partitioning for system level synthesis of integrated circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Jürgen Teich,et al.  Partitioning of processor arrays: a piecewise regular approach , 1993, Integr..

[16]  Edward A. Lee,et al.  Scheduling strategies for multiprocessor real-time DSP , 1989, IEEE Global Telecommunications Conference, 1989, and Exhibition. 'Communications Technology for the 1990s and Beyond.

[17]  Kalyanmoy Deb,et al.  Towards a Quick Computation of Well-Spread Pareto-Optimal Solutions , 2003, EMO.

[18]  Ed F. Deprettere,et al.  Multi-processor system design with ESPAM , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[19]  Michael Randolph Garey,et al.  Johnson: "computers and intractability , 1979 .

[20]  Maryline Chetto,et al.  Dynamic scheduling of real-time tasks under precedence constraints , 1990, Real-Time Systems.

[21]  Andrew S. Tanenbaum,et al.  Structured computer organization, 5th Edition , 2005 .

[22]  Edward G. Coffman,et al.  Computer and job-shop scheduling theory , 1976 .

[23]  Jürgen Teich,et al.  Performance analysis and optimization of mixed asynchronous synchronous systems , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  Gilbert Christopher Sih,et al.  Multiprocessor scheduling to account for interprocessor communication , 1992 .

[25]  Massoud Pedram,et al.  Power minimization in IC design: principles and applications , 1996, TODE.

[26]  Jürgen Teich,et al.  Efficient architecture/compiler co-exploration for ASIPs , 2002, CASES '02.

[27]  Carl Steidley,et al.  Computer organization/architecture: a threaded top-down design , 1988, CSC '88.

[28]  Minjoong Rim,et al.  Representing conditional branches for high-level synthesis applications , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[29]  S. C. Johnson.  Hierarchical clustering schemes , 1967, Psychometrika.

[30]  Fadi J. Kurdahi,et al.  Hierarchical design space exploration for a class of digital systems , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[31]  Petru Eles,et al.  Performance estimation for embedded systems with data and control dependencies , 2000, Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518).

[32]  Kai Richter,et al.  Compositional scheduling analysis using standard event models , 2004 .

[33]  Pierre N. Robillard,et al.  Scheduling with earliest start and due date constraints , 1971 .

[34]  Giorgio Rizzoni,et al.  An Architecture for Exploring Large Design Spaces , 1998, AAAI/IAAI.

[35]  Ken Tindell,et al.  ADDING TIME-OFFSETS TO SCHEDULABILITY ANALYSIS , 1994 .

[36]  Nicolas Halbwachs,et al.  Synchronous Programming of Reactive Systems , 1992, CAV.

[37]  W. A. Horn.  Some simple scheduling algorithms , 1974 .

[38]  Jürgen Teich.  Synthesis and Optimization of Digital Hardware/Software Systems , 2001 .

[39]  Christopher W. Fraser,et al.  BURG: fast optimal instruction selection and tree parsing , 1992, SIGP.

[40]  Dake Liu,et al.  Power consumption estimation in CMOS VLSI chips , 1994, IEEE J. Solid State Circuits.

[41]  Lothar Thiele,et al.  Embedded Software in Network Processors - Models and Algorithms , 2001, EMSOFT.

[42]  Catherine H. Gebotys,et al.  Optimal synthesis of multichip architectures , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[43]  J. R. Jackson.  SCHEDULING A PRODUCTION LINE TO MINIMIZE MAXIMUM TARDINESS , 1955 .

[44]  Alexandru Turjan,et al.  System design using Khan process networks: the Compaan/Laura approach , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[45]  Balakrishnan Krishnamurthy,et al.  An Improved Min-Cut Algonthm for Partitioning VLSI Networks , 1984, IEEE Transactions on Computers.

[46]  Hugo De Man,et al.  Data routing: a paradigm for efficient data-path synthesis and code generation , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.

[47]  Jürgen Teich,et al.  Control generation in the design of processor arrays , 1991, J. VLSI Signal Process..

[48]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .

[49]  Greg Snider,et al.  Spacewalker: Automated Design Space Exploration for Embedded Computer Systems , 2001 .

[50]  Marco Laumanns,et al.  Analysis and applications of evolutionary multiobjective optimization algorithms , 2003 .

[51]  Bernd Baumgarten,et al.  Petri-Netze - Grundlagen und Anwendungen , 1990 .

[52]  Sharad Malik,et al.  Performance analysis of embedded software using implicit path enumeration , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[53]  Ed F. Deprettere,et al.  Exploring Embedded-Systems Architectures with Artemis , 2001, Computer.

[54]  Edward A. Lee,et al.  Software Synthesis from Dataflow Graphs , 1996 .

[55]  David A. Patterson,et al.  Computer Organization & Design: The Hardware/Software Interface , 1993 .

[56]  David Lorge Parnas,et al.  Priority Scheduling Versus Pre-Run-Time Scheduling , 2004, Real-Time Systems.

[57]  Peter Marwedel,et al.  OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming , 1994, EURO-DAC '94.

[58]  Scott W. Ambler,et al.  The Elements of UML(TM) 2.0 Style , 2005 .

[59]  Peter J. Ashenden,et al.  The Designer's Guide to VHDL , 1995 .

[60]  Hermann Kopetz,et al.  Real-time systems , 2018, CSC '73.

[61]  R. K. Ursem.  Multi-objective Optimization using Evolutionary Algorithms , 2009 .

[62]  Sumit Gupta,et al.  SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits , 2004 .

[63]  Tobias Blickle,et al.  Theory of evolutionary algorithms and application to system synthesis , 1997 .

[64]  Andrew W. Appel,et al.  Modern Compiler Implementation in Java , 1997 .

[65]  Hans Liebig,et al.  Mikroprozessortechnik und Rechnerstrukturen , 2006 .

[66]  M. S. Harris.  Computer-aided design techniques for low power sequential logic circuits , 1998 .

[67]  Giovanni De Micheli,et al.  Partitioning of functional models of synchronous digital systems , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[68]  Pierre G. Paulin,et al.  CodeSyn : A Retargetable Code Synthesis System , 1997 .

[69]  Chung-Kuan Cheng,et al.  Ratio cut partitioning for hierarchical designs , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[70]  Clifford Liem,et al.  Retargetable Compilers for Embedded Core Processors , 1997, Springer US.

[71]  Jianwen Zhu,et al.  Specification and Design of Embedded Systems , 1998, Informationstechnik Tech. Inform..

[72]  Eugene L. Lawler,et al.  Optimal Sequencing of a Single Machine Subject to Precedence Constraints , 1973 .

[73]  P. Marwedel,et al.  A New Synthesis Algorithm for the MIMOLA Software System , 1986, 23rd ACM/IEEE Design Automation Conference.

[74]  Donald E. Thomas,et al.  Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench , 1989 .

[75]  Rainer Leupers,et al.  Code optimization techniques for embedded processors - methods, algorithms, and tools , 2000 .

[76]  Robert A. Walker,et al.  A Survey of high-level synthesis systems , 1991 .

[77]  Jörg Henkel,et al.  An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[78]  Vincenzo Catania,et al.  A framework for design space exploration of parameterized VLSI systems , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[79]  Markku Renfors,et al.  The maximum sampling rate of digital filters under hardware speed constraints , 1981 .

[80]  Nikil D. Dutt,et al.  A Unified code generation approach using mutation scheduling , 1994, Code Generation for Embedded Processors.

[81]  Edward A. Ashcroft,et al.  Proving Assertions about Parallel Programs , 1975, J. Comput. Syst. Sci..

[82]  Susan L. Graham,et al.  A new method for compiler code generation , 1978, POPL '78.

[83]  Thomas Lengauer,et al.  Combinatorial algorithms for integrated circuit layout , 1990, Applicable theory in computer science.

[84]  Emile H. L. Aarts,et al.  Improved force-directed scheduling in high-throughput digital signal processing , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[85]  Alexandru Nicolau,et al.  Register Allocation, Renaming and Their Impact on Fine-Grain Parallelism , 1991, LCPC.

[86]  Jürgen Teich,et al.  3D exploration of software schedules for DSP algorithms , 1999, CODES '99.

[87]  Luca Benini,et al.  Combining Simulation and Formal Methods for System-Level Performance Analysis , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[88]  Gary L. Miller,et al.  The Complexity of Coloring Circular Arcs and Chords , 1980, SIAM J. Algebraic Discret. Methods.

[89]  Lui Sha,et al.  Priority Inheritance Protocols: An Approach to Real-Time Synchronization , 1990, IEEE Trans. Computers.

[90]  Xavier Gandibleux,et al.  The Supported Solutions Used as a Genetic Information in a Population Heuristics , 2001, EMO.

[91]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[92]  Joseph A. Fisher,et al.  Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.

[93]  Krzysztof Kuchcinski,et al.  Time-energy design space exploration for multi-layer memory architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[94]  Rolf Ernst,et al.  Experiments with low-level speculative computation based on multiple branch prediction , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[95]  E. F. Girczyc,et al.  Loop winding--a data flow approach to functional pipelining , 1987 .

[96]  P. Stravers.  Embedded system design , 1994 .

[97]  Vijay K. Madisetti.  VLSI Digital Signal Processors: An Introduction to Rapid Prototyping and Design Synthesis , 1995 .

[98]  Jane W.-S. Liu.  Real-Time Systems , 2000, Encyclopedia of Algorithms.

[99]  Gérard Berry,et al.  The Esterel Synchronous Programming Language: Design, Semantics, Implementation , 1992, Sci. Comput. Program..

[100]  Gary William Grewal,et al.  An integrated approach to retargetable code generation , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.

[101]  Andreas Fauth.  Beyond tool-specific machine descriptions , 1994, Code Generation for Embedded Processors.

[102]  Shuvra S. Bhattacharyya,et al.  Efficient techniques for clustering and scheduling onto embedded multiprocessors , 2006, IEEE Transactions on Parallel and Distributed Systems.

[103]  Imtiaz Ahmad,et al.  Synthesis of application-specific multiprocessor systems , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[104]  Yuan Xie,et al.  Allocation and scheduling of conditional task graph in hardware/software co-synthesis , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[105]  Luca Benini,et al.  Regression Models for Behavioral Power Estimation , 1998, Integr. Comput. Aided Eng..

[106]  Rainer Leupers,et al.  Retargetable Code Generation for Digital Signal Processors , 1997, Springer US.

[107]  Eckart Zitzler,et al.  Evolutionary algorithms for multiobjective optimization: methods and applications , 1999 .

[108]  Charles E. Taylor.  Adaptation in Natural and Artificial Systems: An Introductory Analysis with Applications to Biology, Control, and Artificial Intelligence. Complex Adaptive Systems.John H. Holland , 1994 .

[109]  Bart Kienhuis,et al.  Design space exploration of stream-based dataflow architectures: methods and tools , 1999 .

[110]  Jörg Henkel,et al.  System-level exploration for Pareto-optimal configurations in parameterized systems-on-a-chip , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[111]  Daniel Gajski,et al.  Design Tools for Intelligent Silicon Compilation , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[112]  Ed F. Deprettere,et al.  An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures , 1997, ASAP.

[113]  Matthias Gries,et al.  Methods for evaluating and covering the design space during early design development , 2004, Integr..

[114]  Paul Hilfinger,et al.  A Compiler for Application-Specific Signal Processors , 1989 .

[115]  Alan Burns,et al.  Applying new scheduling theory to static priority pre-emptive scheduling , 1993, Softw. Eng. J..

[116]  Sharad Malik,et al.  Developing Architectural Platforms: A Disciplined Approach , 2002, IEEE Des. Test Comput..

[117]  Gregory J. Chaitin,et al.  Register allocation and spilling via graph coloring , 2004, SIGP.

[118]  Praveen K. Murthy,et al.  Memory Management for Synthesis of DSP Software , 2006 .

[119]  Marco Laumanns,et al.  Performance assessment of multiobjective optimizers: an analysis and review , 2003, IEEE Trans. Evol. Comput..

[120]  An evolutionary approach to system-level synthesis , 1997, CODES.

[121]  Andy D. Pimentel,et al.  A systematic approach to exploring embedded system architectures at multiple abstraction levels , 2006, IEEE Transactions on Computers.

[122]  J. M. Moore.  An n Job, One Machine Sequencing Algorithm for Minimizing the Number of Late Jobs , 1968 .

[123]  Steven R. Vegdahl.  Phase coupling and constant generation in an optimizing microcode compiler , 1982, MICRO 15.

[124]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[125]  G. Constantinides,et al.  Fault Tolerance Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques ? , 2003 .

[126]  Yuri Gurevich,et al.  Evolving algebras 1993: Lipari guide , 1995, Specification and validation methods.

[127]  Wolfgang Reisig,et al.  A Primer in Petri Net Design , 1992, Springer Compass International.

[128]  Gilbert Syswerda,et al.  The Application of Genetic Algorithms to Resource Scheduling , 1991, International Conference on Genetic Algorithms.

[129]  Christian Haubelt,et al.  Task-accurate performance modeling in SystemC for real-time multi-processor architectures , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[130]  Keshab K. Parhi,et al.  High-level DSP synthesis using concurrent transformations, scheduling, and allocation , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[131]  Edsger W. Dijkstra,et al.  Cooperating sequential processes , 2002 .

[132]  M. Golumbic.  Algorithmic graph theory and perfect graphs , 1980 .

[133]  Timo Hämäläinen,et al.  UML-based multiprocessor SoC design framework , 2006, TECS.

[134]  Frank Bellosa,et al.  Process cruise control: event-driven clock scaling for dynamic power management , 2002, CASES '02.

[135]  Shuvra S. Bhattacharyya,et al.  Systematic exploitation of data parallelism in hardware synthesis of DSP applications , 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[136]  Ing-Jer Huang,et al.  Generating instruction sets and microarchitectures from applications , 1994, ICCAD.

[137]  Peter Marwedel,et al.  Tree-based mapping of algorithms to predefined structures , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[138]  Daniel Kästner.  Retargetable postpass optimisation by integer linear programming , 2000 .

[139]  Wayne E. Smith.  Various optimizers for single‐stage production , 1956 .

[140]  Petru Eles,et al.  Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

[141]  Christian Haubelt,et al.  A system-level approach to hardware reconfigurable systems , 2005, ASP-DAC.

[142]  Gérard Berry,et al.  The foundations of Esterel , 2000, Proof, Language, and Interaction.

[143]  Pascal Raymond,et al.  The synchronous data flow programming language LUSTRE , 1991, Proc. IEEE.

[144]  Keshab K. Parhi,et al.  Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding , 1991, IEEE Trans. Computers.

[145]  John P. Lehoczky,et al.  Fixed priority scheduling of periodic task sets with arbitrary deadlines , 1990, [1990] Proceedings 11th Real-Time Systems Symposium.

[146]  Robert R Henry.  Graham-Glanville Code Generators , 1999 .

[147]  Hugo De Man,et al.  Power exploration for data dominated video applications , 1996, ISLPED '96.

[148]  Peter Zepter.  Programmgestützter Entwurf integrierter Schaltungen für die digitale Nachrichtenübertragung aus Datenflussbeschreibungen , 1996 .

[149]  P. A. Subrahmanyam,et al.  Hardware/software partitioning for multi-function systems , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[150]  Shuvra S. Bhattacharyya,et al.  Software synthesis from the dataflow interchange format , 2005, SCOPES '05.

[151]  Alfred V. Aho,et al.  Code Generation for Expressions with Common Subexpressions , 1977, J. ACM.

[152]  J. E. Mitchell,et al.  Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[153]  M.C. McFarland.  Using Bottom-Up Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral Descriptions , 1986, 23rd ACM/IEEE Design Automation Conference.

[154]  R. Composano,et al.  Path-based scheduling for synthesis , 1990, Twenty-Third Annual Hawaii International Conference on System Sciences.

[155]  Alice C. Parker,et al.  SOS: Synthesis of application-specific heterogeneous multiprocessor systems , 2001, J. Parallel Distributed Comput..

[156]  Gilbert Syswerda,et al.  Uniform Crossover in Genetic Algorithms , 1989, ICGA.

[157]  Alice C. Parker,et al.  The high-level synthesis of digital systems , 1990, Proc. IEEE.

[158]  John R. Ellis,et al.  Bulldog: A Compiler for VLIW Architectures , 1986 .

[159]  Jürgen Teich,et al.  Design space characterization for architecture/compiler co-exploration , 2001, CASES '01.

[160]  J. Robinson,et al.  Review: Martin Davis, Hilary Putnam, A Computing Procedure for Quantification Theory , 1966, Journal of Symbolic Logic (JSL).

[161]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[162]  R.K. Gupta,et al.  System-level synthesis using re-programmable components , 1992, [1992] Proceedings The European Conference on Design Automation.

[163]  Jürgen Teich,et al.  Multidimensional Exploration of Software Implementations for DSP Algorithms , 2000, J. VLSI Signal Process..

[164]  William Stallings,et al.  Operating Systems: Internals and Design Principles , 1991 .

[165]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[166]  Sandeep Neema,et al.  System-level synthesis of adaptive computing systems , 2001 .

[167]  Lawrence. Davis,et al.  Handbook Of Genetic Algorithms , 1990 .

[168]  Niraj K. Jha,et al.  MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[169]  Tadao Murata,et al.  Petri nets: Properties, analysis and applications , 1989, Proc. IEEE.

[170]  Sharad Malik,et al.  A Survey of Optimization Techniques Targeting Low Power VLSI Circuits , 1995, 32nd Design Automation Conference.

[171]  Andy D. Pimentel,et al.  Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems , 2002, Embedded Processor Design Challenges.

[172]  Roni Potasman.  Percolation-based compiling for evaluation of parallelism and hardware design trade-offs , 1991 .

[173]  T. C. Hu.  Parallel Sequencing and Assembly Line Problems , 1961 .

[174]  Daniel Gajski,et al.  System clock estimation based on clock slack minimization , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[175]  M. Potkonjak,et al.  Synthesis Of Application Specific Programmable Processors , 1997, Proceedings of the 34th Design Automation Conference.

[176]  Alice C. Parker,et al.  MAHA: A Program for Datapath Synthesis , 1986, 23rd ACM/IEEE Design Automation Conference.

[177]  Gilles Kahn,et al.  The Semantics of a Simple Language for Parallel Programming , 1974, IFIP Congress.

[178]  Shuvra S. Bhattacharyya,et al.  Parameterized dataflow modeling for DSP systems , 2001, IEEE Trans. Signal Process..

[179]  Kazutoshi Wakabayashi,et al.  Global scheduling independent of control dependencies based on condition vectors , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[180]  J.C. Lopez,et al.  The design space layer: supporting early design space exploration for core-based designs , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[181]  Luciano Lavagno,et al.  Metropolis: An Integrated Electronic System Design Environment , 2003, Computer.

[182]  Dan Hildebrand,et al.  An Architectural Overview of QNX , 1992, USENIX Workshop on Microkernels and Other Kernel Architectures.

[183]  A. Hashimoto,et al.  Wire routing by optimizing channel assignment within large apertures , 1971, DAC '71.

[184]  David Harel,et al.  Statecharts: A Visual Formalism for Complex Systems , 1987, Sci. Comput. Program..

[185]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[186]  Howard Trickey,et al.  Flamel: A High-Level Hardware Compiler , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[187]  N.K. Jha,et al.  CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[188]  Vincenzo Catania,et al.  Design space exploration methodologies for IP-based system-on-a-chip , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[189]  Edward A. Lee,et al.  Scheduling dynamic dataflow graphs with bounded memory using the token flow model , 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[190]  Wei-Chung Hsu,et al.  Code scheduling and register allocation in large basic blocks , 1988 .

[191]  Jean J. Labrosse,et al.  MicroC/OS-II: The Real Time Kernel , 1998 .

[192]  Gert Goossens,et al.  Embedded software in real-time signal processing systems: design technologies , 1997, Proc. IEEE.

[193]  Massoud Pedram,et al.  Power Simulation and Estimation in VLSI Circuits , 2000, The VLSI Handbook.

[194]  P. Pirsch,et al.  A system level design methodology for the optimization of heterogeneous multiprocessors , 1995 .

[195]  Edward A. Lee,et al.  Minimizing memory requirements for chain-structured synchronous dataflow programs , 1994, Proceedings of ICASSP '94. IEEE International Conference on Acoustics, Speech and Signal Processing.

[196]  David K. Smith.  Theory of Linear and Integer Programming , 1987 .

[197]  P. Le Guernic,et al.  Hybrid dynamical systems theory and the Signal language , 1990 .

[198]  Karsten Strehl,et al.  Symbolic methods applied to formal verification and synthesis in embedded systems design , 2000 .

[199]  A. Tucker,et al.  Coloring a Family of Circular Arcs , 1975 .

[200]  Heinrich Meyr,et al.  LISA-machine description language and generic machine model for HW/SW co-design , 1996, VLSI Signal Processing, IX.

[201]  Tom Shanley,et al.  Infiniband Network Architecture , 2002 .

[202]  Farid N. Najm,et al.  A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[203]  Alice C. Parker,et al.  Sehwa: a software package for synthesis of pipelines from behavioral specifications , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[204]  Joos Vandewalle,et al.  An efficient microcode compiler for application specific DSP processors , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[205]  Niraj K. Jha,et al.  MOCSYN: multiobjective core-based single-chip system synthesis , 1999, DATE '99.

[206]  Matthias Anlauff,et al.  XASM - An Extensible, Component-Based ASM Language , 2000, Abstract State Machines.

[207]  Christian Haubelt.  Automatic model based design space exploration for embedded systems: a system level approach , 2005 .

[208]  Diana Marculescu,et al.  Power and performance evaluation of globally asynchronous locally synchronous processors , 2002, ISCA.

[209]  Hugo De Man,et al.  Global Communication and Memory Optimizing Transformations for Low Power Systems , 1994 .

[210]  Edward Ashford Lee.  A coupled hardware and software architecture for programmable digital signal processors (synchronous data flow) , 1986 .

[211]  Markus Freericks,et al.  Describing instruction set processors using nML , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[212]  Sujit Dey,et al.  Efficient exploration of the SoC communication architecture design space , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[213]  Lothar Thiele,et al.  A framework for evaluating design tradeoffs in packet processing architectures , 2002, DAC '02.

[214]  S. Malik,et al.  Instruction level power analysis and optimization of software , 1996, Proceedings of 9th International Conference on VLSI Design.

[215]  Carlos Valderrama,et al.  Trends in embedded systems technology: an industrial perspective , 1995 .

[216]  Alan C. Tucker,et al.  An Efficient Test for Circular-Arc Graphs , 1980, SIAM J. Comput..

[217]  Luciano Lavagno,et al.  Hardware-software co-design of embedded systems: the POLIS approach , 1997 .

[218]  L. Thiele,et al.  Representation of function variants for embedded system optimization and synthesis , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[219]  Dharma P. Agrawal,et al.  A Framework for Mapping Periodic Real-Time Applications on Multicomputers , 1994, IEEE Trans. Parallel Distributed Syst..

[220]  Joseph Horowitz.  Critical path scheduling : management control through CPM and PERT , 1980 .

[221]  K. Ebcioğlu,et al.  An Efficient Resource-constrained Global Scheduling Technique For Superscalar And Vliw Processors , 1992, [1992] Proceedings the 25th Annual International Symposium on Microarchitecture MICRO 25.

[222]  Jürgen Teich,et al.  Scheduling of partitioned regular algorithms on processor arrays with constrained resources , 1996, Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96.

[223]  Ed F. Deprettere,et al.  A trace transformation technique for communication refinement , 2001, CODES '01.

[224]  Hugo De Man,et al.  Instruction set definition and instruction selection for ASIPs , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.

[225]  Guang R. Gao,et al.  A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs , 1992, CC.

[226]  Bruce D. Shriver,et al.  Some Experiments in Local Microcode Compaction for Horizontal Machines , 1981, IEEE Transactions on Computers.

[227]  Mohamed I. Elmasry,et al.  Global optimization approach for architectural synthesis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[228]  Peter H. Starke,et al.  Analyse von Petri-Netz-Modellen , 1990, Leitfäden und Monographien der Informatik.

[229]  Giovanni De Micheli,et al.  Hardware-software cosynthesis for digital systems , 1993, IEEE Design & Test of Computers.

[230]  Alfred V. Aho,et al.  Optimal Code Generation for Expression Trees , 1976, J. ACM.

[231]  藤倉 俊幸.  組み込みプログラミングノウハウ入門(12)メッセージベーススケジューリングと実装--A Practitioner's Handbook for Real-Time Analysisを読む , 2003 .

[232]  Ronald L. Graham,et al.  Bounds for certain multiprocessing anomalies , 1966 .

[233]  Jan M. Rabaey,et al.  Low-power design of memory intensive functions , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[234]  Robert McNaughton,et al.  Scheduling with Deadlines and Loss Functions , 1959 .

[235]  英晴 天野,et al.  20世紀の名著名論:J. L. Hennessy and D. A. Patterson : Computer Architecture : A Quantitative Approach , 2003 .

[236]  B. Wess.  Automatic instruction code generation based on trellis diagrams , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[237]  Gert Goossens,et al.  Chess: retargetable code generation for embedded DSP processors , 1994, Code Generation for Embedded Processors.

[238]  Kendall Scott,et al.  UML distilled - applying the standard object modeling language , 1997 .

[239]  Christos T. Karamanolis,et al.  Elements of distributed algorithms-modeling and analysis with petri nets Wolfgang Reisig [Book review] , 1999, IEE Proceedings - Software.

[240]  Ahmed Amine Jerraya,et al.  Interactive system-level partitioning with PARTIF , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[241]  U. Aickelin,et al.  The Application of Bayesian Optimization and Classifier Systems in Nurse Scheduling , 2004, PPSN.

[242]  Nikil D. Dutt,et al.  EXPRESSION: a language for architecture exploration through compiler/simulator retargetability , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[243]  Giorgio Buttazzo,et al.  Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications , 1997 .

[244]  Edward A. Lee,et al.  Scheduling synchronous dataflow graphs for efficient looping , 1993, J. VLSI Signal Process..

[245]  Carlos A. Coello Coello,et al.  Handling Constraints in Genetic Algorithms Using Dominance-based Tournaments , 2002 .

[246]  Krithi Ramamritham,et al.  Allocation and Scheduling of Precedence-Related Periodic Tasks , 1995, IEEE Trans. Parallel Distributed Syst..

[247]  Mario Barbacci,et al.  Instruction set processor specifications (ISPS): The notation and its applications , 1981, IEEE Transactions on Computers.

[248]  Susan J. Eggers,et al.  Integrating register allocation and instruction scheduling for RISCs , 1991, ASPLOS IV.

[249]  Todd A. Proebsting.  BURS automata generation , 1995, TOPL.