An embedded flash macro with sub-4ns random-read-access using asymmetric-voltage-biased current-mode sensing scheme

High-performance mobile chips and MCUs require large-capacity and fast-read embedded nonvolatile/Flash memory (eNVM/eFlash) for code and data storage. Current-mode sense amplifiers (CSA) are commonly used in eNVM due to their fast sensing against large bitline (BL) load and small cell read currents. However, conventional CSAs cannot achieve fast random read access time (TAC) due to significant summed read-path input offsets (IOS-SUM). This work proposes an asymmetric-voltage-biased CSA (AVB-CSA) to suppress IOS-SUM and enable high-speed sensing without run-time offset-cancellation operations. A 90nm AVB-CSA 1Mb Flash macro with BL-length test-modes was fabricated. The 512-rows AVB-CSA eFlash macro achieves 3.9ns TAC. The test-mode experiments confirmed that AVB-CSA improves 1.48x in TAC for 2048-rows BL-length. For the first time, a Mb eFlash with long BL achieves sub-4ns TAC.

[1]  Meng-Fan Chang,et al.  An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory , 2011, 2011 IEEE International Solid-State Circuits Conference.

[2]  Meng-Fan Chang,et al.  A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme , 2009, IEEE J. Solid State Circuits.

[3]  Doris Schmitt-Landsiedel,et al.  Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive , 2012, 2012 IEEE International Solid-State Circuits Conference.

[4]  Gyu-Hong Kim,et al.  A 130-nm 0.9-V 66-MHz 8-Mb (256K /spl times/ 32) local SONOS embedded flash EEPROM , 2005 .

[5]  Hideto Hidaka,et al.  40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[6]  Meng-Fan Chang,et al.  A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme , 2009, IEEE Journal of Solid-State Circuits.

[7]  Mark A. Taylor,et al.  A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[8]  Gyu-Hong Kim,et al.  A 130-nm 0.9-V 66-MHz 8-Mb (256K × 32) local SONOS embedded flash EEPROM , 2005, VLSIC 2005.

[9]  Heng-Yuan Lee,et al.  A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability , 2011, 2011 IEEE International Solid-State Circuits Conference.

[10]  Yoichi Yano.  Take the expressway to go greener , 2012, 2012 IEEE International Solid-State Circuits Conference.