Scalable High-Radix Modular Crossbar Switches
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Ron Ho | Ken Mai | Cagla Cakir | Jon K. Lexau
[1] William J. Dally,et al. Microarchitecture of a high radix router , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).
[2] David Blaauw,et al. A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.
[3] Thomas E. Anderson,et al. High speed switch scheduling for local area networks , 1992, ASPLOS V.
[4] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[5] Cyriel Minkenberg,et al. SCOC: High-radix switches made of bufferless clos networks , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).
[6] Nan Jiang,et al. A detailed and flexible cycle-accurate Network-on-Chip simulator , 2013, 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).
[7] Yuval Tamir,et al. High-performance multiqueue buffers for VLSI communication switches , 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.
[8] Dionisios N. Pnevmatikatos,et al. Crossbar NoCs Are Scalable Beyond 100 Nodes , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Samuel P. Morgan,et al. Input Versus Output Queueing on a Space-Division Packet Switch , 1987, IEEE Trans. Commun..
[10] Jung Ho Ahn,et al. Network within a network approach to create a scalable high-radix router microarchitecture , 2012, IEEE International Symposium on High-Performance Comp Architecture.
[11] Y. Tamir,et al. High-performance multi-queue buffers for VLSI communications switches , 1988, ISCA '88.
[12] Pedro López,et al. Towards an efficient switch architecture for high-radix switches , 2006, 2006 Symposium on Architecture For Networking And Communications Systems.
[13] Ron Ho,et al. Modeling and Design of High-Radix On-Chip Crossbar Switches , 2015, NOCS.
[14] Dionisios N. Pnevmatikatos,et al. VLSI micro-architectures for high-radix crossbar schedulers , 2011, Proceedings of the Fifth ACM/IEEE International Symposium.
[15] William J. Dally,et al. Design tradeoffs for tiled CMP on-chip networks , 2006, ICS '06.