Testing Resistive Opens and Bridging Faults Through Pulse Propagation

This paper addresses the problems related to resistive opens and bridging faults that lie out of the most critical paths. These faults cannot be detected by traditional delay fault testing because the induced delay defects are not large enough to result in timing violations when the test rate is equal to the nominal operating frequency. In spite of this problem, resistive opens and bridgings should be detected because they may give rise to reliability problems. To detect them, we propose a testing method that is based on the propagation of pulses within the faulty circuit and that exploits the degraded capability of faulty paths to propagate pulses. The effectiveness of our method is analyzed at the transistor level and compared with the use of reduced clock periods to detect the same class of faults. Results show similar performance in the case of resistive opens and better performance in the case of bridgings. Moreover, the proposed approach is not affected by possible problems in the clock distribution.

[1]  Niklas Sörensson,et al.  An Extensible SAT-solver , 2003, SAT.

[2]  James D. Meindl,et al.  Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.

[3]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[4]  Cecilia Metra,et al.  Interactive presentation: Pulse propagation for the detection of small delay defects , 2007 .

[5]  Guido Gronthoud,et al.  On hazard-free patterns for fine-delay fault testing , 2004, 2004 International Conferce on Test.

[6]  Edward J. McCluskey,et al.  Testing for resistive opens and stuck opens , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[7]  Haihua Yan,et al.  Evaluating the effectiveness of detecting delay defects in the slack interval: a simulation study , 2004, 2004 International Conferce on Test.

[8]  Haihua Yan,et al.  A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI) , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Rosa Rodríguez-Montañés,et al.  Resistance characterization for weak open defects , 2002, IEEE Design & Test of Computers.

[10]  Cecilia Metra,et al.  Pulse propagation for the detection of small delay defects , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[11]  T.W. Williams,et al.  AN ENHANCEMENT TO LSSD AND SOME APPLICATIONS OF LSSD IN RELIABILITY, AVAILABILITY, AND SERVICEABILIT , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

[12]  Keith Baker,et al.  Defect-based delay testing of resistive vias-contacts a critical evaluation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[13]  D. M. H. Walker,et al.  Resistive bridge fault modeling, simulation and test generation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[14]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[15]  Phil Nigh.  The increasing importance of on-line testing to ensure high-reliability products , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[16]  Cecilia Metra,et al.  Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines , 2000, IEEE Trans. Computers.

[17]  Daniel Arumí,et al.  Experimental Characterization of CMOS Interconnect Open Defects , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Sani R. Nassif,et al.  Modeling and analysis of manufacturing variations , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[19]  Adit D. Singh.  A self-timed structural test methodology for timing anomalies due to defects and process variations , 2005, IEEE International Conference on Test, 2005..

[20]  Bernd Becker,et al.  Resistive Bridge fault model evolution from conventional to ultra deep submicron , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[21]  Sreejit Chakravarty.  On the capability of delay tests to detect bridges and opens , 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

[22]  Chulwoo Kim,et al.  Differential Pass Transistor Pulsed Latch , 2005, SoCC.

[23]  Michele Favalli,et al.  Dynamic effects in the detection of bridging faults in CMOS ICs , 1992, J. Electron. Test..

[24]  Kaushik Roy,et al.  Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[25]  Kaushik Roy,et al.  Statistical timing analysis using levelized covariance propagation , 2005, Design, Automation and Test in Europe.

[26]  C. Metra,et al.  A model for transient fault propagation in combinatorial logic , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..