A scalable synchronous system

The performance of the synchronous timing scheme for VLSI-based systems is examined. It is shown that traditional clocking used in this scheme leads to serious performance shortcoming, particularly for submicrometer technologies. A novel mode of clocking is proposed and examined in detail. This clocking mode makes the performance of the synchronous system almost scalable with scaling the feature size of MOS devices. The application of this mode of clocking to H-tree networks, usually used in systolic arrays, is also investigated.<<ETX>>

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