Reconfigurable processing framework for space-time block codes

Space-time block coding has emerged in recent years as a promising research topic to enable future high-speed wireless communications networks and services. A considerable number of authors have developed algorithms and techniques that have been explored in simulations. However, fully implemented systems are rare. This paper considers the use of reconfigurable logic for implementing space-time block coding algorithms, allowing greater coding complexity than traditional DSP implemented systems. In particular, a number of matrix multiplication-style architectures are proposed for implementing channel estimators on FPGA hardware. These are compared in terms of speed and size, and accuracy is compared with a MATLAB simulation. Reconfigurable processing framework for space-time block codes (PDF Download Available). Available from: http://www.researchgate.net/publication/228991771_Reconfigurable_processing_framework_for_space-time_block_codes [accessed Sep 4, 2015].

[1]  Junqiang Sun,et al.  Tms320c6000 cpu and instruction set reference guide , 2000 .

[2]  Petre Stoica,et al.  Space-time block coding for channels with intersymbol interference , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[3]  B. Achiriloaie,et al.  VI REFERENCES , 1961 .

[4]  Arogyaswami Paulraj,et al.  A transmit diversity scheme for channels with intersymbol interference , 2000, 2000 IEEE International Conference on Communications. ICC 2000. Global Convergence Through Communications. Conference Record.

[5]  Siavash M. Alamouti,et al.  A simple transmit diversity technique for wireless communications , 1998, IEEE J. Sel. Areas Commun..

[6]  Ian McLoughlin,et al.  Time reversal space time block coding with channel estimation and synchronisation errors , 2003 .