Pulse stream VLSI circuits and techniques for the implementation of neural networks

[1]  Lawrence D. Jackel,et al.  Application of the ANNA neural network chip to high-speed character recognition , 1992, IEEE Trans. Neural Networks.

[2]  Andreas G. Andreou,et al.  A Contrast Sensitive Silicon Retina with Reciprocal Synapses , 1991, NIPS.

[3]  James A. Simmons,et al.  Acoustic-Imaging Computations by Echolocating Bats: Unification of Diversely-Represented Stimulus Features into Whole Images , 1989, NIPS.

[4]  N. El-Leithy,et al.  Implementation of pulse-coded neural networks , 1988, Proceedings of the 27th IEEE Conference on Decision and Control.

[5]  D. Soo,et al.  A 4-quadrant MOS analog multiplier , 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  J. Bailey,et al.  Why VLSI implementations of associative VLCNs require connection multiplexing , 1988, IEEE 1988 International Conference on Neural Networks.

[7]  Alan F. Murray,et al.  Pulse-Firing Neural Chips for Hundreds of Neurons , 1989, NIPS.

[8]  Hannu Tenhunen,et al.  Fully digital neural network implementation based on pulse density modulation , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[9]  James M. Bower,et al.  Modeling Small Oscillating Biological Networks in Analog VLSI , 1988, NIPS.

[10]  Alan F. Murray,et al.  Pulse arithmetic in VLSI neural networks , 1989, IEEE Micro.

[11]  Alan F. Murray,et al.  Analog VLSI Neural Networks : Pulse Stream Implementations , 1989 .

[12]  Geoffrey E. Hinton,et al.  Learning representations by back-propagating errors , 1986, Nature.

[13]  F ROSENBLATT,et al.  The perceptron: a probabilistic model for information storage and organization in the brain. , 1958, Psychological review.

[14]  Alan F. Murray.  Analogue noise-enhanced learning in neural network circuits , 1991 .

[15]  J. G. Elias,et al.  A neuromorphic impulsive circuit for processing dynamic signals , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[16]  Alan F. Murray,et al.  Asynchronous arithmetic for VLSI neural systems , 1987 .

[17]  James L. McClelland,et al.  Explorations in parallel distributed processing: a handbook of models, programs, and exercises , 1988 .

[18]  Randy H. Katz,et al.  Design of PLL-based clock generation circuits , 1987 .

[19]  H. Martin Reekie,et al.  Pulse-Firing VLSI Neural Circuits for Fast Image Pattern Recognition , 1991 .

[20]  Simon M. Tam,et al.  Implementation and performance of an analog nonvolatile neural network , 1993 .

[21]  Alan F. Murray,et al.  Results from Pulse-Stream VLSI Neural Network Devices , 1991 .

[22]  Jack L. Meador,et al.  Programmable impulse neural circuits , 1991, IEEE Trans. Neural Networks.

[23]  Y. Hirai,et al.  A digital neuro-chip with unlimited connectability for large scale neural networks , 1989, International 1989 Joint Conference on Neural Networks.

[24]  Alan F. Murray,et al.  A Novel Computational and Signalling Method for VLSI Neural Networks , 1987, ESSCIRC '87: 13th European Solid-State Circuits Conference.

[25]  Anthony V. W. Smith,et al.  Implementation of neural networks as CMOS integrated circuits , 1988 .

[26]  Alan F. Murray,et al.  Programmable Analog Pulse-Firing Neural Networks , 1988, NIPS.

[27]  Kimmo Kaski,et al.  Pulse-density modulation technique in VLSI implementations of neural network algorithms , 1990 .

[28]  Alan F. Murray,et al.  Asynchronous VLSI neural networks using pulse-stream arithmetic , 1988 .

[29]  B. Linares-Barranco,et al.  CMOS analog neural network systems based on oscillatory neurons , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[30]  Stephen Churcher,et al.  VLSI neural networks for computer vision , 1993 .

[31]  Michel Steyaert,et al.  Analog VLSI implementation of Neural Networks , 1992 .

[32]  Lionel Tarassenko,et al.  A fast, novel, cascadable design for multi-layer networks , 1991 .

[33]  J. P. Sage,et al.  MNOS/CCD circuits for neural network implementations , 1989, IEEE International Symposium on Circuits and Systems,.

[34]  Tobi Delbrück,et al.  Direction Selective Silicon Retina that Uses Null Inhibition , 1991, NIPS.

[35]  A. E. Owen,et al.  Amorphous silicon analogue memory devices , 1989 .

[36]  J. G. Elias,et al.  A generic algorithm for training networks with artificial dendritic trees , 1992, [Proceedings 1992] IJCNN International Joint Conference on Neural Networks.

[37]  Alan F. Murray,et al.  Innovations in Pulse Stream Neural VLSI : Arithmetic and Communications , 1990 .

[38]  Alan F. Murray,et al.  Analogue CMOS techniques for VLSI neural networks: process invariant circuits and devices , 1991 .

[39]  R. S. Withers,et al.  An artificial neural network integrated circuit based on MNOS/CCD principles , 1987 .

[40]  H. T. Kung.  Why systolic architectures? , 1982, Computer.

[41]  Yasuji Sawada,et al.  Functional abilities of a stochastic logic neural network , 1992, IEEE Trans. Neural Networks.

[42]  Alan F. Murray,et al.  Real-Time Autonomous Robot Navigation Using VLSI Neural Networks , 1990, NIPS.