A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing capture IR-drop, there is a lack of complete capture-safe test generation flows. The paper addresses this problem by proposing a novel and practical capture-safe test generation scheme, featuring (1) reliable capture-safety checking and (2) effective capture-safety improvement by combining X-bit identification & X-filling with low launch- switching-activity test generation. This scheme is compatible with existing ATPG flows, and achieves capture-safety with no changes in the circuit-under-test or the clocking scheme.

[1]  L. Whetsel,et al.  An analysis of power reduction techniques in scan testing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[2]  Rishi Bhooshan.  Novel and Efficient IR-Drop Models for Designing Power Distribution Network for Sub-100nm Integrated Circuits , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[3]  Irith Pomeranz,et al.  Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs , 2006, 2006 IEEE International Test Conference.

[4]  Xiaoqing Wen,et al.  A novel scheme to reduce power supply noise for high-quality at-speed scan testing , 2007, 2007 IEEE International Test Conference.

[5]  Kozo Kinoshita,et al.  A new ATPG method for efficient capture power reduction during scan testing , 2006, 24th IEEE VLSI Test Symposium.

[6]  Srivaths Ravi,et al.  Power-aware test: Challenges and solutions , 2007, 2007 IEEE International Test Conference.

[7]  V. Kamakoti,et al.  A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test , 2007, 2007 IEEE International Test Conference.

[8]  Kenneth M. Butler,et al.  A case study of ir-drop in structured at-speed testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[9]  Kohei Miyase,et al.  XID: Don't care identification of test patterns for combinational circuits , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Vinay Jayaram,et al.  Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[11]  Aiman H. El-Maleh,et al.  An efficient test relaxation technique for synchronous sequential circuits , 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Wenlong Wei,et al.  A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture , 2007, 2007 Asia and South Pacific Design Automation Conference.

[13]  Bashir M. Al-Hashimi,et al.  Power-constrained testing of VLSI circuits , 2003 .

[14]  Guido Gronthoud,et al.  Power Supply Noise in Delay Testing , 2006, 2006 IEEE International Test Conference.