A modified Costas loop for clock recovery and frequency synthesis

A clock recovery circuit that takes advantage of self biasing, and the presence of delayed and advanced versions of the VCO output to increase the phase detector gain has been designed and simulated using a 0.6 /spl mu/m CMOS N-well process. This clock recovery circuit shows a fast response time. In addition to clock recovery, this circuit can be used as a frequency multiplier or synthesizer, without additional circuitry. To reduce jitter, the feedback loop is closed only when there is a control signal to adjust the VCO frequency.

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