Systolic processing architectures using optoelectronic interconnects

Systolic arrays have traditionally provided efficient, high performance execution for computation intensive applications. Despite the extensive research in systolic arrays, system designers must continually incorporate new technological advances to improve node communications, I/O bandwidth, and programmability. This paper presents optoelectronic interconnect as a communication method for systolic arrays in early image processing applications. Optoelectronic interconnects provide potentially high I/O bandwidth required to maintain high utilization rate for systolic arrays. In addition, optoelectronic interconnects provides a two-dimensional focal-plane topology ideal for systolic image processing systems. This paper introduces two new systolic architectures that incorporate integrated optoelectronics to provide an extremely compact, high performance, highly efficient image processing system. Several important early image processing applications developed for these architectures are also described.

[1]  C. Camperi-Ginestet,et al.  High density focal plane signal processing using 3-D vertical interconnects , 1994, Proceedings of 1994 37th Midwest Symposium on Circuits and Systems.

[2]  Robert M. Lougheed,et al.  An Analysis of Computer Architectural Factors Contributing to Image Processor Capacity , 1986, Other Conferences.

[3]  Daniel P. Lopresti,et al.  Architecture of a programmable systolic array , 1988, [1988] Proceedings. International Conference on Systolic Arrays.

[4]  T. J. Fountain.  The use of linear arrays for image processing , 1988, [1988] Proceedings. International Conference on Systolic Arrays.

[5]  D. S. Wills,et al.  A fine-grain, high-throughput architecture using through-wafer optical interconnect , 1994, First International Workshop on Massively Parallel Processing Using Optical Interconnections.

[6]  H. T. Kung.  Why systolic architectures? , 1982, Computer.

[7]  C. Camperi-Ginestet,et al.  Communication through stacked silicon circuitry using integrated thin film InP-based emitters and detectors , 1995, IEEE Photonics Technology Letters.

[8]  Azriel Rosenfeld,et al.  A Pyramid Framework for Early Vision , 1994 .

[9]  Wai-Chi Fang,et al.  VLSI focal-plane array processor for morphological image processing , 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.

[10]  Tarek M. Taha,et al.  Processing architectures for smart pixel systems , 1996 .

[11]  B. Buchanan,et al.  8 x 8 array of thin-film photodetectors vertically electrically interconnected to silicon circuitry , 1995, IEEE Photonics Technology Letters.

[12]  April S. Brown,et al.  SIMPil: an OE integrated SIMD architecture for focal plane processing applications , 1996, Proceedings of Massively Parallel Processing Using Optical Interconnections.

[13]  Ali R. Hurson,et al.  General-purpose systolic arrays , 1993, Computer.

[14]  Eric R. Fossum,et al.  Real-Time Focal-Plane Array Image Processor , 1990, Other Conferences.

[15]  Jean-Luc Basille,et al.  Multilevel Architectures For Image Processing , 1986, Other Conferences.

[16]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .