Single chip video processor for digital HDTV
暂无分享,去创建一个
We have developed a single chip video processor integrated TS decoder, MPEG-2 MP@HL decoder and OSD controller for BS digital broadcasting. The video processor is available for all the formats of digital broadcasting and displays output on the "Hi-Vision" (high-definition) CRT in SDTV as well as HDTV. Also, 4-channel decoding/display and multi-angle broadcasting of digital TV is obtained. It has excellent functions such as seamless display, audio/video (AV) synchronization, error concealment, etc. Adoption of a cooperative processing architecture with hardware and software, pipeline architecture and parallel bus architecture allows flexible support of operating frequency reduction, circuit miniaturization, design simplification, high-performance service of BS digital TV, digital TV broadcasting regulation change and equipment specification change. This single chip video processor is manufactured of 0.25-/spl mu/m four-layer metal CMOS process and the chip size is 10.2 mm/spl times/10.2 mm. The power consumption is 4.5 W when the supply voltage is 2.5 V and operating frequency is 121.5 MHz.
[1] Minoru Tanaka,et al. A cost-effective D-TV system chip set , 1999, 1999 Digest of Technical Papers. International Conference on Consumer Electronics (Cat. No.99CH36277).