Domino Logic Circuit with Reduced Leakage and Improved Noise Margin

As the technology is continuously scaled, leakage currents become a major contributor to the total power dissipation. A reduction in power supply voltage is necessary to reduce dynamic power and avoid reliability problems in deep sub-micron (DSM) regimes. Threshold voltage reduction accompanies supply voltage scaling to maintain the performance, but it exponentially increases the subthreshold leakage currents. Domino logic circuits are extensively used in high performance microprocessors due to their superior speed and area characteristics compared to static CMOS circuits. But they are extremely susceptible to noise and are highly leaky. In this paper, to the standard low-Vth domino logic, an additional control circuit referred as Adaptive Voltage Level (AVL) circuit is used which reduces the voltage fed to the load circuit in order to reduce the leakage power. This technique provides a lesser leakage power and evaluation delay than lowVth technique. Simulation results revealed that the data dependent leakage is less here when compared to low-Vth and dualVth techniques. The noise margin is much improved compared to dual-Vth but at the slight expense of evaluation delay. This technique can be used as an alternative to dual-Vth technique in noisy environments.

[1]  Kevin J. Nowka,et al.  Circuit design techniques for a gigahertz integer microprocessor , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[2]  A. Alvandpour,et al.  A leakage-tolerant multi-phase keeper for wide domino circuits , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

[3]  Mohamed I. Elmasry,et al.  High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[4]  A.P. Chandrakasan,et al.  Dual-threshold voltage techniques for low-power digital circuits , 2000, IEEE Journal of Solid-State Circuits.

[5]  K. Soumyanath,et al.  Robustness of sub-70 nm dynamic circuits: analytical techniques and scaling trends , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[6]  Eby G. Friedman,et al.  Low swing dual threshold voltage domino logic , 2002, GLSVLSI '02.

[7]  Atila Alvandpour,et al.  A sub-130-nm conditional keeper technique , 2002, IEEE J. Solid State Circuits.

[8]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[9]  Tadayoshi Enomoto,et al.  A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications , 2003, IEEE J. Solid State Circuits.

[10]  Eby G. Friedman,et al.  Sleep switch dual threshold Voltage domino logic with reduced standby leakage current , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Massoud Pedram,et al.  Leakage current reduction in CMOS VLSI circuits by input vector control , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Narayanan Vijaykrishnan,et al.  Characterization and modeling of run-time techniques for leakage power reduction , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.