Metamodeling of RFIC integrated inductors using ASITIC simulation data

In this paper, we describe a new method to generate lumped-parameter equivalent-circuit (EC) approximations for on-chip inductors. Nonlinear least-squares fitting is then applied to numerical data obtained from a very large number of single-time ASITIC runs for a given process. Results show significant improvement as compared to the published models. The proposed method should enable the optimization of inductor geometry.

[1]  Stephen P. Boyd,et al.  Simple accurate expressions for planar spiral inductances , 1999, IEEE J. Solid State Circuits.

[2]  Hans-Martin Rein,et al.  Modeling substrate effects in the design of high-speed Si-bipolar ICs , 1996, IEEE J. Solid State Circuits.

[3]  T.H. Lee,et al.  A physical model for planar spiral inductors on silicon , 1996, International Electron Devices Meeting. Technical Digest.

[4]  Michiel Steyaert,et al.  A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors , 1997, IEEE J. Solid State Circuits.

[5]  J.N. Burghartz,et al.  Multilevel-spiral inductors using VLSI interconnect technology , 1996, IEEE Electron Device Letters.

[6]  Stephen P. Boyd,et al.  Optimization of inductor circuits via geometric programming , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[7]  Peter R. Kinget,et al.  An analytical model of planar inductors on lowly doped silicon substrates for analog design up to 3G , 1996 .