The performance of IEEE floating-point operators on FPGAs

The introduction of very large FPGA has made it practical to implement multiple double precision floating-point units on a single FPGA making them a suitable platform for the acceleration of complex numerical problems such as computational fluid dynamics (CFD). Using a combination of architectural reconfigurability, multiple numeric processors and variable-precision arithmetic the efficiency and performance of such an accelerator can be investigated. The first stage in this work is the development of floating-point units suitable for implementation on FPGA. This work reports on the design of fully IEEE compliant, double precision multipliers and adders implemented on state of the art FPGA. Performance data are presented and compared with data on similar devices reported by both industry and academia.