Finite Precision Arithmetic in Singular Value Decomposition Architectures

Abstract : The singular value decomposition (SVD) is an important matrix algorithm which has many applications in signal processing. However, its use has been limited due to its computational complexity. Several computer architectures have been proposed to compute the SVD using arrays of parallel processors. This thesis derives requirements for the precision of arithmetic units ;(AUs) used in SVD arrays and compare the resource requirements of several architectures. The results are based on the assumption that we are operating on matrices of quantized data. Since the matrices have quantization errors, it is shown that their singular values will have quantization errors which are as large as the data errors. To compute the number of bits needed in SVD AUs, it is required that the AUs have enough bits to keep the round-off errors of the SVD computation smaller than the quantization errors. This analysis shows that we need essentially the same number of bits for either the Hestenes or Jacobi SVD algorithms. If the matrix has been scaled to prevent overflows and if we use properly rounded arithmetic, CORDIC and fixed point AUs require 8 fewer bits than floating point AUs. Our computations indicate that 32 bit floating point AUs are useful only for small arrays of 8-bit data. For 100-by-100 arrays of 16 bit data we need 40-bit floating point AUs. 32-bit fixed point AUs can be used in SVD arrays for large 8-bit matrices or moderate size 16-bit arrays.