UPaRC: u ltra-fast p ower- a ware r econfiguration c ontroller

Dynamically reconfigurable architectures, which can offer high performance, are increasingly used in different domains. High-speed reconfiguration process can be carried out by operating at high frequency but can also augment the power consumption. Thus the effort on increasing performance by accelerating the reconfiguration should take into account power consumption constraints. In this paper, we present an ultra-fast power-aware reconfiguration controller (UPaRC) to boost the reconfiguration throughput up to 1.433 GB/s. UPaRC can not only enhance the system performance, but also auto-adapt to various performance and consumption conditions. This could enlarge the range of applications and optimize for each selected application during run-time. An investigation of reconfiguration bandwidths at different frequencies and with different bitstream sizes are experimentally quantified and presented. The power consumption measurements are also realized to emphasize energy-efficiency of UPaRC over state-of-the-art reconfiguration controllers---up to 45 times more efficient.

[1]  Mark Nelson,et al.  The Data Compression Book , 2009 .

[2]  Axel Jantsch,et al.  Run-time Partial Reconfiguration speed investigation and architectural design space exploration , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[3]  Ikbel Belaid,et al.  New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA , 2010, Int. J. Reconfigurable Comput..

[4]  R. Viswanath.  Thermal Performance Challenges from Silicon to Systems , 2000 .

[5]  José L. Núñez-Yáñez,et al.  Dynamic Reconfiguration Optimisation with Streaming Data Decompression , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[6]  Jürgen Becker,et al.  Power estimation and power measurement of Xilinx Virtex FPGAs: trade-offs and limitations , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[7]  Jürgen Becker,et al.  Dynamic and Partial FPGA Exploitation , 2007, Proceedings of the IEEE.

[8]  François Duhem,et al.  FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA , 2011, ARC.

[9]  José Luis Núñez,et al.  Gbit/s lossless data compression hardware , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Luigi Carro,et al.  A new reconfigurable clock-gating technique for low power SRAM-based FPGAs , 2011, 2011 Design, Automation & Test in Europe.