On the current error based sampled-data iterative learning control with reduced memory capacity

The design of iterative learning controller (ILC) requires to store the system input, output or control parameters of previous trials for generating the input of the current trial. In order to apply the iterative learning controller for a real application and reduce the memory size for implementation, a current error based sampled-data proportional-derivative (PD) type iterative learning controller is proposed for control systems with initial resetting error, input disturbance and output measurement noise in this paper. The proposed iterative learning controller is simple and effective. The first contribution in this paper is to prove the learning error convergence via a rigorous technical analysis. It is shown that the learning error will converge to a residual set if a forgetting factor is introduced in the controller. All the theoretical results are also shown by computer simulations. The second main contribution is to realize the iterative learning controller by a digital circuit using a field programmable gate array (FPGA) chip applied to repetitive position tracking control of direct current (DC) motors. The feasibility and effectiveness of the proposed current error based sampled-data iterative learning controller are demonstrated by the experiment results. Finally, the relationship between learning performance and design parameters are also discussed extensively.