Randomized routing of virtual connections in essentially nonblocking log N-depth networks

An optimal N/spl times/N circuit switching network with /spl theta/(N/spl times/N) bandwidth has a lower bound of /spl theta/(N/spl middot/log N) hardware, which includes all crosspoints, bits of memory and logic gates, and a lower bound of /spl theta/(logN) set-up time. To date no known self-routing circuit switching networks with explicit constructions achieve these lower bounds. The authors consider a randomized routing algorithm on a class of circuit switching networks called "extended dilated banyans". It is proven that the blocking probability of an individual connection request is O[log/sub b/ N/spl middot/(k/d)/sup d/], where d is the dilation factor and k is a constant. With a dilation of /spl theta/(log log N) and a loading >

[1]  Ted H. Szymanski,et al.  Performance analysis of channel sharing in multistage ATM switching networks , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[2]  V. Benes,et al.  Mathematical Theory of Connecting Networks and Telephone Traffic. , 1966 .

[3]  Sajal K. Das,et al.  Book Review: Introduction to Parallel Algorithms and Architectures : Arrays, Trees, Hypercubes by F. T. Leighton (Morgan Kauffman Pub, 1992) , 1992, SIGA.

[4]  Bruce M. Maggs,et al.  On-line algorithms for path selection in a nonblocking network , 1990, STOC '90.

[5]  Leslie G. Valiant,et al.  Universal schemes for parallel communication , 1981, STOC '81.

[6]  W. Hoeffding On the Distribution of the Number of Successes in Independent Trials , 1956 .

[7]  Ted H. Szymanski,et al.  On the Universality of Multipath Multistage Interconnection Networks , 1989, J. Parallel Distributed Comput..

[8]  János Komlós,et al.  An 0(n log n) sorting network , 1983, STOC.

[9]  Dharma P. Agrawal,et al.  Graph Theoretical Analysis and Design of Multistage Interconnection Networks , 1983, IEEE Transactions on Computers.

[10]  Kenneth E. Batcher,et al.  Sorting networks and their applications , 1968, AFIPS Spring Joint Computing Conference.

[11]  Ted H. Szymanski,et al.  On the Permutation Capability of Multistage Interconnection Networks , 1987, IEEE Transactions on Computers.

[12]  Tony T. Lee A modular architecture for very large packet switches , 1990, IEEE Trans. Commun..

[13]  Alan Huang,et al.  Starlite: a wideband digital switch , 1991 .

[14]  Marc Snir,et al.  The Performance of Multistage Interconnection Networks for Multiprocessors , 1983, IEEE Transactions on Computers.

[15]  Janak H. Patel Performance of Processor-Memory Interconnections for Multiprocessors , 1981, IEEE Transactions on Computers.

[16]  Claude E. Shannon,et al.  Memory requirements in a telephone exchange , 1950 .

[17]  Allan Borodin,et al.  Routing, merging and sorting on parallel models of computation , 1982, STOC '82.

[18]  R.R. Kock Increasing the size of a network by a constant factor can increase performance by more than a constant factor , 1988, [Proceedings 1988] 29th Annual Symposium on Foundations of Computer Science.

[19]  David G. Cantor,et al.  On non-blocking switching networks , 1971, Networks.

[20]  Nicholas Pippenger,et al.  On Crossbar Switching Networks , 1975, IEEE Trans. Commun..

[21]  Debasis Mitra,et al.  Randomized parallel communications on an extension of the omega network , 1987, JACM.