A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing

This paper outlines the RC-filtered stress-decoupled (RCSD) 4T2R nonvolatile TCAM (nvTCAM) with the following benefits: 1) reduced NVM-stress; 2) reduced ML parasitic load; and 3) suppression of match-line (ML) leakage current from match cells. The RCSD-4T2R cell achieves a 6× reduction in NVM-stress, a 2× increase in maximum wordlength, and a 2× reduction in search delay. In this paper, we also outline two search schemes, referred to as dynamic source-line pulse controlled (DSL-PC) search and dataline-pulse controlled (DL-PC) search, which were developed specifically for the RCSD-4T2R nvTCAM. We fabricated a 128 × 32 b RCSD-4T2R nvTCAM macro with HfO ReRAM using a 180 nm CMOS process. Using the DSL-PC and DL-PC schemes, the measured search delay of the RCSD-4T2R nvTCAM macro was 1.2 ns under typical VDD.

[1]  Hanyu Takahiro,et al.  Fabrication of a 99%-Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierarchical Power Gating for a Massively-Parallel Full-Text-Search Engine , 2014 .

[2]  Tien-Fu Chen,et al.  An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices , 2009, IEEE Journal of Solid-State Circuits.

[3]  Meng-Fan Chang,et al.  A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme , 2009, IEEE J. Solid State Circuits.

[4]  Meng-Fan Chang,et al.  RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94x reduction in restore energy for frequent-off instant-on applications , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[5]  Tetsuo Endoh,et al.  10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[6]  Heng-Yuan Lee,et al.  A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability , 2011, 2011 IEEE International Solid-State Circuits Conference.

[7]  Hideto Hidaka,et al.  40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[8]  Yukio Hayakawa,et al.  An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput , 2012, IEEE Journal of Solid-State Circuits.

[9]  Meng-Fan Chang,et al.  19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[10]  Makoto Kitagawa,et al.  A 4Mb conductive-bridge resistive memory with 2.3GB/s read-throughput and 216MB/s program-throughput , 2011, 2011 IEEE International Solid-State Circuits Conference.

[11]  Hiroyuki Kawai,et al.  A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS , 2013, IEEE Journal of Solid-State Circuits.

[12]  Mahesh Mehendale,et al.  8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[13]  Peilin Song,et al.  1Mb 0.41 µm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing , 2013, 2013 Symposium on VLSI Circuits.

[14]  Doris Schmitt-Landsiedel,et al.  Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive , 2012, 2012 IEEE International Solid-State Circuits Conference.

[15]  Shoji Ikeda,et al.  A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[16]  Meng-Fan Chang,et al.  Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme , 2014, IEEE Journal of Solid-State Circuits.

[17]  Meng-Fan Chang,et al.  An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros , 2015, IEEE Journal of Solid-State Circuits.

[18]  Meng-Fan Chang,et al.  A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time , 2012, 2012 IEEE International Solid-State Circuits Conference.

[19]  Meng-Fan Chang,et al.  Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications , 2012, IEEE Journal of Solid-State Circuits.

[20]  Hugh P. McAdams,et al.  An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at VDD=0V with <400ns wakeup and sleep transitions , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[21]  Yoichi Yano Take the expressway to go greener , 2012, 2012 IEEE International Solid-State Circuits Conference.

[22]  Meng-Fan Chang,et al.  ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

[23]  Meng-Fan Chang,et al.  RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94x reduction in restore energy for frequent-off instant-on applications , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).