论文信息 - A 12 bit Continuous-Time /spl Sigma//spl Delta/ modulator with 400MHz clock and low jitter sensitivity in 0.13 /spl mu/m CMOS

A 12 bit Continuous-Time /spl Sigma//spl Delta/ modulator with 400MHz clock and low jitter sensitivity in 0.13 /spl mu/m CMOS

A wide bandwidth Continuous-Time /spl Sigma//spl Delta/ lowpass ADC with a 4-bit internal quantizer is presented. The converter is implemented in a pure digital 0.13 /spl mu/m CMOS. It achieves 76dB Dynamic Range over 12MHz signal bandwidth tolerating up to 20ps RMS clock jitter. Operated at 400MHz the power consumption is 70mW from a 1.5V supply. The ADC has been designed to be tolerant to excess-loop delay and clock jitter. The 4/sup th/-order loop-filter is based on OpAmp-RC structure.

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