Delay model for dynamically switching coupled RLC interconnects

With the evolution of integrated circuit technology, the interconnect parasitics can be the limiting factor in high speed signal transmission. With increasing frequency of operation, length of interconnect and fast transition time of the signal, the RC models are not sufficient to estimate the delay accurately. To mitigate this problem, accurate delay models for coupled interconnects are very much required. This paper proposes an analytical model for estimating propagation delay in lossy coupled RLC interconnect lines for simultaneously switching scenario. To verify the proposed model, the analytical results are compared with those of FDTD and SPICE results for the two cases of inputs switching under consideration. An average error of 2.07% is observed which shows an excellent agreement with SPICE simulation and FDTD computations.

[1]  David Blaauw,et al.  Modeling and analysis of crosstalk noise in coupled RLC interconnects , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  T. Sakurai,et al.  Approximation of wiring delay in MOSFET LSI , 1983, IEEE Journal of Solid-State Circuits.

[3]  James D. Meindl,et al.  Compact distributed RLC interconnect models. I. Single line transient, time delay, and overshoot expressions , 2000 .

[4]  Guoqing Chen,et al.  An RLC interconnect model based on fourier analysis , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  James D. Meindl,et al.  Compact distributed RLC interconnect models - part IV: unified models for time delay, crosstalk, and repeater insertion , 2003 .

[6]  C. Paul Incorporation of terminal constraints in the FDTD analysis of transmission lines , 1994 .

[7]  James D. Meindl,et al.  Compact distributed RLC interconnect models - part III: transients in single and coupled lines with capacitive load termination , 2003 .

[8]  James D. Meindl,et al.  Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel networks , 2000 .

[9]  Brajesh Kumar Kaushik,et al.  Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[11]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  J.A. Davis,et al.  Compact physical models for multilevel interconnect crosstalk in gigascale integration (GSI) , 2004, IEEE Transactions on Electron Devices.

[13]  Brajesh Kumar Kaushik,et al.  Crosstalk analysis and repeater insertion in crosstalk aware coupled VLSI interconnects , 2006 .

[14]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.

[15]  Andrew B. Kahng,et al.  An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Yehea I. Ismail,et al.  Equivalent Elmore delay for RLC trees , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Anestis Dounavis,et al.  Closed-Form Delay and Crosstalk Models for $RLC$ On-Chip Interconnects Using a Matrix Rational Approximation , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Takayasu Sakurai,et al.  Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .