Performance improvement of global interconnects using combined techniques of low swing transceiver and buffer insertion in nano technologies

Delay and power of the global interconnects are the most important parameters in the performance of VLSI circuits, particularly in nano scales. This paper presents a combined technique from a low swing transceiver and buffer insertion scheme. By this technique, we can reduce both the delay of global interconnects and also the power. In the other hand, we use a low swing transceiver to reduce the power of the interconnect and use the buffer insertion scheme for the interconnect between the driver and receiver to reduce the delay. Therefore, by this technique, we can reduce the powedelay product in nano scales.

[1]  Hui-Fen Huang,et al.  Global interconnect width and spacing optimization for latency, bandwidth and power dissipation , 2005, IEEE Transactions on Electron Devices.

[2]  Min Tang,et al.  Optimization of global interconnects in high performance VLSI circuits , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[3]  Shuming Chen,et al.  A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[4]  K. Banerjee,et al.  A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation , 2004, IEEE Transactions on Electron Devices.

[5]  Jason Cong,et al.  An efficient technique for device and interconnect optimization in deep submicron designs , 1998, ISPD '98.

[6]  M. Mehran,et al.  A tapered partitioning method for “delay energy product” optimization in global interconnects , 2007, 2007 50th Midwest Symposium on Circuits and Systems.

[7]  Kaustav Banerjee,et al.  Inductance aware interconnect scaling , 2002, Proceedings International Symposium on Quality Electronic Design.

[8]  Maryam Shojaei Baghini,et al.  Low power current mode receiver with inductive input impedance , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

[9]  George Varghese,et al.  Low-swing on-chip signaling techniques: effectiveness and robustness , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Hui Zhang,et al.  Low-swing interconnect interface circuits , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[11]  Ralph H. J. M. Otten,et al.  Are wires plannable? , 2001, SLIP '01.

[12]  Liu Yong,et al.  A low swing differential signaling circuit for on-chip global interconnects , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.