MCML gate design for standard cell library

This paper evaluates the impact of MCML gate design specifications into a standard cell library. The tradeoff between design parameters (bias current, voltage swing and noise margin) and maximum fate operating frequency are taken into account. We demonstrate that in MCML standard cell library the voltage swing and noise margin should be uniform for all logic gates. All evaluations were done over a 0.6μm CMOS technology. The transistor sizing necessary to achieve the required noise margin makes small voltage swings not attractive to MCML gate design. The increase of bias current also requires larger transistors as a result the propagation delay gain is no more significant for higher bias current. In the studied case, this value is around 100μA. The analysis of the library composition demonstrates that functions of four inputs have better performance if they are implemented using two inputs cascaded gates instead of a dedicated four inputs gate.