Design and Evaluation of A Low-Voltage, Process-Variation-Tolerant SRAM Cache in 90nm CMOS Technology

This thesis presents a novel six-transistor SRAM intended for advanced microprocessor cache application. The objectives are to reduce power consumption through scaling the supply voltage and to design a SRAM that is fully process-variation-tolerant, utilizing separate read and write access ports as well as exploiting asymmetry. Traditional six-transistor SRAM is designed and its strengths and weaknesses are discussed in detail. Afterwards, a new SRAM technology developed in the division of Electronic Devices, Linkoping University is proposed and its capabilities and drawbacks are illustrated deeply. Subsequently, the impact of mismatch and process variation on both standard 6T and proposed asymmetric 6T SRAM cells is investigated. Eventually, the cells are compared regarding the voltage scalability, stability, and tolerability to variations in process parameters. It is shown that the new cell functions in 430mV while maintaining acceptable SNM margin in all process corners. It is also demonstrated that the proposed SRAM is fully process-variation-tolerant. Additionally, a dual-V t asymmetric 6T cell is introduced having wide SNM margin comparable with that of conventional 6T cell such that it is capable of functioning in 580mV.

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