A 3.6 dB NF, 6 GHz band CMOS LNA with 3.6 mW power consumption

This work presents a fully integrated 6 GHz LNA designed using 0.12 mum IBM CMOS technology. The amplifier consumes only 3.6 mW dc power with 1.2 V supply voltage, and features a 11 dB power gain and 3.6 dB noise figure at the frequency of 6 GHz. Additionally, it achieves -11 dBm of input referred 1 dB compression point and -0.5 dBm of IIP3. At the same time input and output matching are better than -15 and -10 dB, respectively. It is shown that capacitance connected between the gate and ground of the common source transistor can be used for improving the performance of the LNA

[1]  G. Boeck,et al.  A 2.14 GHz, 0.78 dB noise figure CMOS low noise amplifier , 2005, The European Conference on Wireless Technology, 2005..

[2]  Mourad N. El-Gamal,et al.  Gain and frequency controllable sub-1 V 5.8 GHz CMOS LNA , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[3]  E. H. Westerwick.  A 5 GHz band CMOS low noise amplifier with a 2.5 dB noise figure , 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

[4]  P. Wambacq,et al.  A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS , 2004, IEEE Journal of Solid-State Circuits.

[5]  Georg Böck,et al.  RF-CMOS Integrated Circuits for Wireless Communications , 2006 .

[6]  M. Steyaert,et al.  A 5 GHz CMOS low-noise amplifier with inductive ESD protection exceeding 3 kV HBM , 2004, Proceedings of the 30th European Solid-State Circuits Conference.