Threshold electromigration failure time and its statistics for Cu interconnects

Integrated circuit chip metallization reliability under use conditions is extrapolated from failure distributions of test structures tested under accelerated conditions. Lognormally plotted electromigration failure time distributions for via/line contact configurations with no redundant conductive path usually display two features that are different from failure time distributions for configurations that have well-defined redundant conductive paths. First, the failure times are more widely distributed (larger standard deviation or σ), and second, the left portion of the distribution (early failures) bends downward (if the sample size is large enough) as the failure times become shorter, in contrast to the straight line behavior that is usually observed for structures with good redundancy. The downward deviation from a straight line distribution erodes the goodness of fit relative to the commonly used two-parameter (t50,σ) lognormal distribution model, and the large σ produces a lifetime projection under u...