A Three-Stage Load-Balancing Switch

Recently there has been a great deal of interest in load-balancing switches due to their simple architecture and high bandwidth. In this paper we propose a three-stage load- balancing switch along with output load-balancing to address the mis-sequencing problem. We show that our proposed scheme provides a delay guarantee bounded by the delay of an OQ switch with the same input traffic plus a constant while achieving 100% throughput for admissible traffic with (sigma, rho) -upper constraint.

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