Low power sensor node processor architecture

This paper presents a low power solution for sensor node processor architecture, where an asynchronous processor has been integrated with a number of peripherals in a quite unique fashion. The paper describes the most important architectural and design issues and presents the implementation results.

[1]  B. Otis,et al.  PicoRadios for wireless sensor networks: the next challenge in ultra-low power design , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[2]  Rajeevan Amirtharajah,et al.  Self-powered signal processing using vibration-based power generation , 1998, IEEE J. Solid State Circuits.

[3]  Gu-Yeon Wei,et al.  An ultra low power system architecture for sensor network applications , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[4]  David E. Culler,et al.  System architecture for wireless sensor networks , 2003 .

[5]  R.W. Brodersen,et al.  A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.

[6]  Goran Panic,et al.  Architecture of a Power-Gated Wireless Sensor Node , 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

[7]  Rajit Manohar,et al.  SNAP: a Sensor-Network Asynchronous Processor , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

[8]  Skandar Basrour,et al.  Wireless sensor network node with asynchronous architecture and vibration harvesting micro power generator , 2005, sOc-EUSAI '05.

[9]  John A. Stankovic,et al.  Radio-triggered wake-up capability for sensor networks , 2004, Proceedings. RTAS 2004. 10th IEEE Real-Time and Embedded Technology and Applications Symposium, 2004..