DECIDER: A Decision Diagram Based Hierarchical Test Generation System

Current paper presents a hierarchical test pattern generation system that uses register-transfer level VHDL and gate-level EDIF netlist descriptions as inputs. The system includes appropriate interfaces to synthesize Decision Diagram (DD) models, a DD based test pattern generator and a fault simulator to evaluate the quality of the generated tests. In the paper, the structure of the system is presented. Additionally, representation of different design abstraction levels using decision diagrams is explained. The performance of the system is compared to other state-of-the-art tools for sequential circuit test generation.

[1]  Raimund Ubar,et al.  Test Synthesis with Alternative Graphs , 1996, IEEE Des. Test Comput..

[2]  Janak H. Patel,et al.  Architectural level test generation for microprocessors , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Elizabeth M. Rudnick,et al.  Sequential Circuit Test Generation in a Genetic Algorithm Framework , 1994, 31st Design Automation Conference.

[4]  Elizabeth M. Rudnick,et al.  Fast sequential circuit test generation using high-level and gate-level techniques , 1998, Proceedings Design, Automation and Test in Europe.

[5]  Raimund Ubar,et al.  Hierarchical Test Generation with Multi-Level Decision Diagram , 1998 .

[6]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[7]  Janak H. Patel,et al.  Hierarchical test generation under intensive global functional constraints , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[8]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .