Source-code-level Transformation and APT-Driven Parallelism Pre-processes for Embedded System Automated Design

A particular pre-processing framework for embedded system design automation is presented in this paper. The main motivation of this framework is to construct a unified internal platform that bridges the gap from the original system application input to the intermediate kernel representation in hardware/software (HW/SW) co-design. To cope with this issue, novel algorithms for the transformation from C specification to hierarchical control data flow graph (HCDFG) and parallelism optimization are employed in this paper, which satisfy the front-end requirements of HW/SW partitioning in the whole design. In particular, a novel model named abstract parallel tree (APT) is emphatically presented in detail to offer a theoretic support for the implementation of parallelism optimization. Finally, the summary of experimental implementations is presented and the feasibility of this framework is validated

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