A 0.7 /spl mu/m linear BiCMOS/DMOS technology for mixed-signal/power applications

A 0.7 /spl mu/m BiCMOS technology is described. The baseline process offers digital and analog CMOS, a variety of bipolar devices, poly resistors, poly-poly capacitors, Schottky diodes, noise isolation, and 3 levels of metal. Power DMOS transistors with 60 V (R/sub sp/=0.90 m/spl Omega//spl middot/cm/sup 2/) down to 16 V (R/sub sp/=0.34 m/spl Omega//spl middot/cm/sup 2/) performance are available as an option in the process.

[1]  John P. Erdeljac,et al.  A 2.0 micron BiCMOS process including DMOS transistors for merged linear ASIC analog/digital/power applications , 1992, [Proceedings] APEC '92 Seventh Annual Applied Power Electronics Conference and Exposition.