DCT/IDCT processor design for HDTV applications

Transform coders, in particular the discrete cosine transform (DCT), have been widely used in the implementation of low-rate codecs for video compression. The DCT has become an integral part of several standards such as MPEG, and CCITT Recommendations H. 261 and H.263. For real time implementation of the DCT at MPEG rates, general purpose DSPs have been proposed. However, with the imminent arrival of high definition television and the considerably higher sample rates (75 MHz sampling frequencies) and higher throughput requirements, processors specific to the DCT (ASICs) with highly parallel and/or pipelined architectures have been reported. The use of such processors can be justified only if they result in a cost effective implementation. We describe a simple but cost effective design of a combined DCT/IDCT processor. The implementation uses a parallel architecture that exploits the symmetry properties in the DCT/IDCT algorithm and requires only simple hardwired multipliers. Clocking at 100 MHz, the processor is capable of handling real-time HDTV signals. The core area of the processor has been minimized while keeping the I/O requirements simple. Finite wordlength and accuracy studies have been carried out to ensure that the resulting implementation conforms to existing standards (H.261).