A software development tool chain for a reconfigurable processor

Reconfigurable processors, in which part of the instruction set can be defined dynamically at run time, hold the promise to cover a broad span of applications with low cost and good performance. They are a possible solution to the silicon provider’s dilemma between specialization, resulting in fewer parts per design and thus higher costs, and generalization, resulting in lower performance. However, their widespread use requires new powerful CAD tools that enable system designers, mostly trained in using software languages for implementation, to exploit the reconfigurable instruction set. This paper is devoted to an in-depth discussion of how the wellknown, very powerful, but relatively inflexible gcc tool suite can be adapted to support a new reconfigurable architecture. This extension of the basic 32/16 bit MIPS architecture, described more in detail in [5, 6], features several aspects that make it appealing for a variety of baseband Digital Signal Processing tasks:

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