Message Sequence Charts for Assertion-based Verification

This paper presents a technique to generate SystemVerilog assertions directly from high-level specification constructs of Message Sequence Charts (MSC) to bridge the productivity gap for current complex designs. Commercial solutions for automated assertion generation do not currently exist. We argue that our technique does span across the hardware/software continuum, allowing it to be applied to both hardware and software components of embedded designs. Keywords-assertion; message sequence chart; verification; simulation; response-checking

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