Timing yield estimation with clock network correlations by propagating discrete probability distributions

Timing yield, in conjunction with other types of yield, directly affects profit; under-estimation is as bad as over-estimation, because large amount of time is unnecessarily spent to increase small amount of timing yield. The correlation that stems from clock network, when ignored, turns out to be one of the reasons of under-estimation in clocked sequential circuit. Three sources of topological correlation are identified; the key problem is to determine the correlations we can ignore without sacrificing accuracy so that we keep run time within control, which is addressed in this paper. A prototype tool was implemented with gate delay modeled as discrete probability distribution; experiments with benchmark circuits show that, compared to Monte Carlo simulation, speedup is 75× with 0.53% difference of timing yield on average.