Design of a 12-bit 2 MS/s 12 mW pipelined SAR ADC in CMOS 0.18 μm technology for CZT-based imaging system

This paper presents a 12-bit 2 MS/s pipelined successive approximation register (SAR) ADC for CZT-based imaging system. The proposed ADC is divided into a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. The first-stage MDAC has a gain of 16 instead of the usual gain of 64, which considerably minimizes the power dissipation of residue amplifier. The second-stage 8-bit SAR ADC employs unit bridge capacitor split-capacitor architecture aiming to reduce the load capacitance of residue amplifier so as to minimize the power dissipation of the proposed ADC. Moreover, a code-randomized calibration algorithm is proposed to improve the linearity of the second-stage 8-bit split-capacitor SAR ADC. In addition, several radiation-hardened-by-design techniques are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μ m mixed-signal 1.8 V/3.3 V process and occupied a core area of 0.71 mm2. The proposed pipelined SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 63.2 dB at 2 MS/s sampling rate and consumes 12 mW power in total. The figure of merit (FoM) of the proposed ADC is 5.06 pJ/conversion-step.