An architecture for the estimation of higher order cumulants

To achieve real-time performance in signal processing applications that require the estimation of higher order statistics, it is necessary to introduce parallel processing and pipelining. The authors present a two stage VLSI architecture for the computation of all the non-negative lags of the cumulants of a real, one-dimensional data sequence. All the non-negative lags of the moments, up to the fourth order, are computed first by a triangular array, based on the indirect block-type estimation approach (C. L. Nikias and M. R. Roghuveer, 1987). The second and fourth order moments are then used to compute the fourth order cumulants using additional processors. A systematic algorithm-to-architectures synthesis methodology facilitated the design of both parts of the architecture and their optimal space and data flow matching.<<ETX>>

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