A 8∶1 static frequency divider operating up to 34 GHz in 0.13-µm CMOS technology
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[1] J. Lee,et al. A 40 Gb/s clock and data recovery circuit in 0.18 /spl mu/m CMOS technology , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[2] Jean-Olivier Plouchart,et al. A power-efficient 33 GHz 2:1 static frequency divider in 0.12-/spl mu/m SOI CMOS , 2003, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003.
[3] Michael M. Green,et al. High-frequency CML clock dividers in 0.13-/spl mu/m CMOS operating up to 38 GHz , 2005, IEEE Journal of Solid-State Circuits.
[4] Viswanathan Subramanian,et al. Fully integrated high efficiency K-band PA in 0.18 µm CMOS technology , 2009, 2009 SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference (IMOC).
[5] R. Evans,et al. A 40 GHz Power Efficient Static CML Frequency Divider in 0.13-μm CMOS Technology for High Speed Millimeter-Wave Wireless Systems , 2008, 2008 4th IEEE International Conference on Circuits and Systems for Communications.
[6] Behzad Razavi,et al. A 40 Gb/s clock and data recovery circuit in 0.18 μm CMOS technology , 2003 .
[7] H.-D. Wohlmuth,et al. A high sensitivity static 2:1 frequency divider up to 27GHz in 120nm CMOS , 2002, Proceedings of the 28th European Solid-State Circuits Conference.
[8] Changhua Cao. A power efficient 26-GHz 32:1 static frequency divider in 130-nm bulk CMOS , 2005 .
[9] Viswanathan Subramanian,et al. 60 GHz SiGe HBT Chip Set for High Speed Wireless Communication Systems , 2008 .
[10] A. Rylyakov,et al. A broadband 44-GHz frequency divider in 90-nm CMOS , 2005, IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05..