ESD protection design for the 45-V pLDMOS-SCR (p-n-p-arranged) devices with source-discrete distributions

An evaluation of electrostatic-discharge (ESD) reliability by changing the source-end layout of 45-V HV pLDMOS devices is investigated in this paper. After testing and systematic analysis, it can be found that a traditional pLDMOS sample is always very weak in ESD issues (It2= 0.107-A). At the same time, if a pLDMOS with a stripe type embedded SCR (p-n-p-arrangement in the drain-end); the corresponding secondary breakdown-current value can be improved about 501.9% as comparing with a pure pLDMOS. Furthermore, when a pLDMOS-SCR possesses the p-n-p-arranged stripe type and source discrete technique, the trigger voltage (Vt1) values of these samples are all about 45-V ~ 47-V. Next, the holding-voltage (Vh) values were slowly increased with the OD-rows number decreased. Also, the secondary breakdown-current (It2) capabilities are upgraded to 3-A ~ 4-A except for S_DIS 3. Eventually, it can be concluded that a discrete distribution in the source region of a pLDMOS-SCR will upgrade the anti-ESD capability effectively as this embedded SCR is p-n-p-arranged in the drain side.

[1]  Chun-Yu Lin,et al.  Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology , 2015, 2015 IEEE Nanotechnology Materials and Devices Conference (NMDC).

[2]  S. Trinh,et al.  Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width-scaling , 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

[3]  Xiaofeng Fan,et al.  A novel low voltage base-modulated SCR ESD device with low latch-up risk , 2009, 2009 31st EOS/ESD Symposium.

[4]  Ming-Dou Ker,et al.  ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC , 2016, IEEE Transactions on Electron Devices.

[5]  Ming-Dou Ker,et al.  Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Raj Verma Purakh,et al.  0.18μm BCD technology platform with performance and cost optimized fully isolated LDMOS , 2015, 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

[7]  Yao-Wen Chang,et al.  A non-typical latch-up event on HV ESD protection , 2014, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2014.