An interconnect model for storage array on Chip

In this paper, a model of transmission line based on Laplace transform is presented; this model could be computed repeatedly used by second or more-order frequency function, in which a signal of voltage difference between stimulus and response is proposed. It is possible to calculate iterative discrete convolution with computer instead of analytic continuous convolution, because the mentioned voltage signal reach to zero when the time variation reach to infinity. The model could be used in delay specificity analysis in large-scale storage array. The model is more approaching to physical analysis and HSPICE simulation results than traditional Elmore model.

[1]  Chandramouli V. Kashyap,et al.  Closed-form delay and slew metrics made easy , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Andrew B. Kahng,et al.  An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Chris C. N. Chu,et al.  Fitted Elmore delay: a simple and accurate interconnect delay model , 2002, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Andrew B. Kahng,et al.  An analytical delay model for RLC interconnects , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[5]  Sarma B. K. Vrudhula,et al.  Variational interconnect delay metrics for statistical timing analysis , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[6]  N. Ranganathan,et al.  A linear time algorithm for wire sizing with simultaneous optimization of interconnect delay and crosstalk noise , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[7]  Xin Li,et al.  Behavioral modeling for analog system-level simulation by wavelet collocation method , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[8]  David Blaauw,et al.  Variational delay metrics for interconnect timing analysis , 2004, Proceedings. 41st Design Automation Conference, 2004..

[9]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[10]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .

[11]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..