Electromigration has been a major reliability concern for nano-interconnects in CMOS applications. With further CMOS miniaturization, the cross-sectional area of nano-interconnects is further scaled resulting in a significant increase of current densities. It has been shown that $j_{max}$ of copper interconnects degrades abruptly at scaled linewidths, predicting increased susceptibility to electromigration. Nevertheless, there is still a dilemma given that the electromigration metrics are typically obtained from electromigration tests on single isolated interconnects and may not be readily translated into metrics for interconnect networks of CMOS designs, which is key for enabling realistic reliability predictions at system-level. In this paper, we demonstrate a physics-based system-level electromigration modelling platform aiming to address the shortcomings of the standard of practice for electromigration compliance checks during the design phase and enhance the accuracy of lifetime predictions from a system viewpoint. The framework is specifically applied to the case of PDN for a 3 nm technology node.