Scan Test Planning for Power Reduction

Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can be used for reducing the power consumption during test. Here, we present an efficient algorithm for the automated generation of a test plan that keeps fault coverage as well as test time, while significantly reducing the amount of wasted energy. A fault isolation table, which is usually used for diagnosis and debug, is employed to accurately determine scan chains that can be disabled. The algorithm was successfully applied to large industrial circuits and identifies a very large amount of excess pattern shift activity.

[1]  Patrick Girard,et al.  A modified clock scheme for a low power BIST test pattern generator , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[2]  S. Asano,et al.  The design and implementation of a first-generation CELL processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[3]  Hans-Joachim Wunderlich,et al.  Minimized Power Consumption for Scan-Based BIST , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[4]  Irith Pomeranz,et al.  Techniques for minimizing power dissipation in scan and combinational circuits during test application , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Janusz Rajski,et al.  Logic BIST for large industrial designs: real issues and case studies , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[6]  B. Koneman,et al.  LFSR-Coded Test Patterns for Scan Designs , 1993 .

[7]  Nur A. Touba,et al.  Reducing power dissipation during test using scan chain disable , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[8]  Yervant Zorian,et al.  A distributed BIST control scheme for complex VLSI devices , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[9]  Peter Wohl,et al.  Scalable selector architecture for X-tolerant deterministic BIST , 2004, Proceedings. 41st Design Automation Conference, 2004..

[10]  Bernard Courtois,et al.  Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers , 1995, IEEE Trans. Computers.

[11]  Olivier Coudert,et al.  On solving covering problems , 1996, DAC '96.

[12]  Nilanjan Mukherjee,et al.  Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm , 2002, Proceedings. International Test Conference.

[13]  Jaume Segura,et al.  Test and Reliability: Partners in IC Manufacturing, Part 1 , 1999, IEEE Des. Test Comput..

[14]  Janusz Rajski,et al.  Test response compactor with programmable selector , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[15]  João Paulo Teixeira,et al.  Low Power BIST by Filtering Non-Detecting Vectors , 1999, European Test Workshop 1999 (Cat. No.PR00390).

[16]  T. Larrabee Creating Small Fault Dictionaries , 1998 .

[17]  Bashir M. Al-Hashimi,et al.  Power-conscious test synthesis and scheduling , 2003, IEEE Design & Test of Computers.

[18]  Jaume Segura,et al.  Test and Reliability: Partners in IC Manufacturing, Part 2 , 1999, IEEE Des. Test Comput..

[19]  Janak H. Patel,et al.  New Techniques for Deterministic Test Pattern Generation , 1999, J. Electron. Test..

[20]  Hans-Joachim Wunderlich,et al.  BIST Power Reduction Using Scan-Chain Disable in the Cell Processor , 2006, 2006 IEEE International Test Conference.

[21]  Paul H. Bardell,et al.  Self-Testing of Multichip Logic Modules , 1982, International Test Conference.

[22]  Mack W. Riley,et al.  Testability features of the first-generation CELL processor , 2005, IEEE International Conference on Test, 2005..

[23]  Krishnendu Chakrabarty,et al.  Design and analysis of compact dictionaries for diagnosis in scan-BIST , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[24]  Arnaud Virazel,et al.  Design of routing-constrained low power scan chains , 2004 .

[25]  B. L. Keller,et al.  Built-in self-test support in the IBM engineering design system , 1990 .

[26]  Tracy Larrabee,et al.  Creating small fault dictionaries [logic circuit fault diagnosis] , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[27]  Hans-Joachim Wunderlich Multiple distributions for biased random test patterns , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[28]  Lee Whetsel,et al.  Adapting scan architectures for low power operation , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).