Low-power area-efficient SAR ADCs with on-chip voltage reference

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[1]  Yeonam Yoon,et al.  A 6-bit 0.81mW 700-MS/s SAR ADC with sparkle-code correction, resolution enhancement, and background window width calibration , 2018, 2018 IEEE Custom Integrated Circuits Conference (CICC).

[2]  David Blaauw,et al.  A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems , 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

[3]  Yung-Hui Chung,et al.  An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Hsin-Shu Chen,et al.  11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[5]  Atila Alvandpour,et al.  A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS , 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Rui Paulo Martins,et al.  A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC , 2016, IEEE Journal of Solid-State Circuits.

[7]  Arthur H. M. van Roermund,et al.  A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[8]  Boris Murmann,et al.  A 14-Bit 30-MS/s 38-mW SAR ADC Using Noise Filter Gear Shifting , 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Arthur H. M. van Roermund,et al.  A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference , 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

[10]  Jason Hu,et al.  An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

[11]  Zhihua Wang,et al.  A fully integrated wireless SoC for in-body pH and temperature continuous monitoring , 2015, 2015 International SoC Design Conference (ISOCC).

[12]  Wei-Hsin Tseng,et al.  A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters , 2016, IEEE Journal of Solid-State Circuits.

[13]  Arthur H. M. van Roermund,et al.  15.4 A 0.8V 10b 80kS/s SAR ADC with duty-cycled reference generation , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[14]  Yong Lian,et al.  A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip , 2009, IEEE Journal of Solid-State Circuits.

[15]  Chih-Cheng Hsieh,et al.  A 0.4V 2.02fJ/conversion-step 10-bit hybrid SAR ADC with time-domain quantizer in 90nm CMOS , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

[16]  David Blaauw,et al.  FOCUS: Key building blocks and integration strategy of a miniaturized wireless sensor node , 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

[17]  Nan Sun,et al.  A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS , 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

[18]  G. Iannaccone,et al.  A Sub-1 V, 10 ppm/°C, Nanopower Voltage Reference Generator , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[19]  Soon-Jyh Chang,et al.  A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS , 2011, IEEE Asian Solid-State Circuits Conference 2011.

[20]  Malcolm J. Hawksford,et al.  Identifica-tion of Discrete Volterra Series Using Maximum Length Sequences , 1996 .

[21]  Pja Pieter Harpe Ultra-low power analog-digital converters for IoT , 2017 .

[22]  David Blaauw,et al.  An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring , 2015, IEEE Journal of Solid-State Circuits.

[23]  Changzhi Li,et al.  A Subthreshold-MOSFETs-Based Scattered Relative Temperature Sensor Front-End With a Non-Calibrated ±2.5°C 3σ Relative Inaccuracy From -40°C to 100°C. , 2013 .

[24]  Giuseppe Iannaccone,et al.  A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference , 2011, IEEE Journal of Solid-State Circuits.

[25]  Ralf Brederlow,et al.  An Ultra Low Power Bandgap Operational at Supply From 0.75 V , 2012, IEEE Journal of Solid-State Circuits.

[26]  Y. Ogushi,et al.  [Analog-digital conversion]. , 1973, Kokyu to junkan. Respiration & circulation.

[27]  Massimo Alioto IoT: Bird’s Eye View, Megatrends and Perspectives , 2017 .

[28]  Pieter Harpe,et al.  A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver , 2019, IEEE Journal of Solid-State Circuits.

[29]  Chorng-Kuang Wang,et al.  A 8-bit 500-KS/s low power SAR ADC for bio-medical applications , 2007, 2007 IEEE Asian Solid-State Circuits Conference.

[30]  Jon Guerber,et al.  Merged capacitor switching based SAR ADC with highest switching energy-efficiency , 2010 .

[31]  David Blaauw,et al.  A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V , 2012, IEEE Journal of Solid-State Circuits.

[32]  T. Karnik,et al.  Area-efficient linear regulator with ultra-fast load regulation , 2005, IEEE Journal of Solid-State Circuits.

[33]  N. P. van der Meijs,et al.  A 26 $\mu$ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios , 2011, IEEE Journal of Solid-State Circuits.

[34]  Chun-Huat Heng,et al.  A 3-Lead ECG-on-Chip with QRS Detection and Lossless Compression for Wireless Sensors , 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

[35]  I. Elumalai A Capacitance-Based Reference Scheme for a 14b-Linear, 100 MS/s SAR-Assisted Pipeline ADC , 2013 .

[36]  Arthur H. M. van Roermund,et al.  11.1 An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[37]  Jan Craninckx,et al.  A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[38]  Chulwoo Kim,et al.  A 100-nW 9.1-ENOB 20-kS/s SAR ADC for Portable Pulse Oximeter , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[39]  Yu-Hsuan Tu,et al.  A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC , 2016, IEEE Journal of Solid-State Circuits.

[40]  Hsin-Shu Chen,et al.  A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique , 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[41]  Bang-Sup Song,et al.  Threshold-voltage temperature drift in ion-implanted MOS transistors , 1982, IEEE Transactions on Electron Devices.

[42]  Eric A. M. Klumperink,et al.  A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s , 2010, IEEE Journal of Solid-State Circuits.

[43]  Paul Bustamante,et al.  Ultra low-power smart medical sensor node for in-body Biomonitoring , 2013, 2013 IEEE 15th International Conference on e-Health Networking, Applications and Services (Healthcom 2013).

[44]  Eitake Ibaragi,et al.  A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS , 2013, IEEE Journal of Solid-State Circuits.

[45]  Jan Craninckx,et al.  A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization , 2018, IEEE Journal of Solid-State Circuits.

[46]  Xiaoyan Wang,et al.  A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[47]  Chung-Ming Huang,et al.  A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18µm CMOS , 2010, 2010 Symposium on VLSI Circuits.

[48]  Arthur H. M. van Roermund,et al.  A 0.9V-VDD sub-nW resistor-less duty-cycled CMOS voltage reference in 65nm for IoT , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[49]  David Blaauw,et al.  A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[50]  Arthur H. M. van Roermund,et al.  A 7.1fJ/conv.-step 88dB-SFDR 12b SAR ADC with energy-efficient swap-to-reset , 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

[51]  Prakash Harikumar,et al.  Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[52]  Nobutaka Kuroki,et al.  1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs , 2013, IEEE Journal of Solid-State Circuits.

[53]  Yusuf Leblebici,et al.  A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS , 2013, IEEE Journal of Solid-State Circuits.

[54]  Arthur H. M. van Roermund,et al.  A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step , 2013, IEEE Journal of Solid-State Circuits.

[55]  Nan Sun,et al.  A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique , 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

[56]  Soon-Jyh Chang,et al.  A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure , 2010, IEEE Journal of Solid-State Circuits.

[57]  Chulwoo Kim,et al.  Edge pursuit comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC , 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

[58]  Ron Kapusta,et al.  A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS , 2018, IEEE Journal of Solid-State Circuits.

[59]  Jan Craninckx,et al.  A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

[60]  Hui Wang,et al.  A 420 fW self-regulated 3T voltage reference generator achieving 0.47%/V line regulation from 0.4-to-1.2 V , 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

[61]  Chih-Cheng Hsieh,et al.  A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[62]  Günter Zimmer,et al.  Threshold-voltage sensitivity of ion-implanted m.o.s. transistors due to process variations , 1974 .

[63]  Melanie Hartmann,et al.  Design Of Analog Cmos Integrated Circuits , 2016 .

[64]  Pieter Harpe,et al.  A 7.1-fJ/Conversion-Step 88-dB SFDR SAR ADC With Energy-Free “Swap To Reset” , 2017, IEEE Journal of Solid-State Circuits.

[65]  F. Borghetti,et al.  A Programmable 10b up-to-6MS/s SAR-ADC Featuring Constant-FoM with On-Chip Reference Voltage Buffers , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.