A parallel trimming method of offset reduction for comparators and amplifiers

In this work, we have proposed a parallel trimming method for analogue circuits based on a tunnel analogue memory in CMOS standard technology. This method can be used to trim simultaneously a large number of circuits with a global control of trimming and a local control of charge injection automatically. The experimental results show that this parallel trimming is efficient and exploitable for CMOS standard technology.<<ETX>>