Activity-Monitoring Completion-Detection (AMCD): a new single rail approach to achieve self-timing

A new method for designing single rail asynchronous circuits is studied. It utilises additional circuitry to monitor the activity of nodes within combinational logic blocks. When all transitions have halted a completion signal is generated. Details of the circuit and design methodology are given and the influence of glitches on the proposed circuit is discussed. Three different levels of granularity are investigated. Experimental physical layout of the circuit with extracted and back-annotated simulation results is provided. The proposed approach results in faster operation than synchronous circuits with minimum circuit overhead incurred.

[1]  V. I. Varshavsky,et al.  Asynchronous interaction in massively parallel computing systems , 1995, Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing.

[2]  Scott Hauck,et al.  Asynchronous design methodologies: an overview , 1995, Proc. IEEE.

[3]  I. I. Shagurin,et al.  Physical approach to CMOS module self-timing , 1990 .

[4]  Bruce E. Briley.  Some New Results on Average Worst Case Carry , 1973, IEEE Transactions on Computers.

[5]  E. Grass,et al.  Activity-monitoring completion-detection (AMCD): a new approach to achieve self-timing , 1996 .

[6]  Eckhard Grass,et al.  Asynchronous circuits based on multiple localised current-sensing completion detection , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.

[7]  Mark Horowitz,et al.  Self-timed logic using current-sensing completion detection (CSCD) , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[8]  N. R. Poole.  Self-timed logic circuits , 1994 .