Drop-shock reliability improvement of embedded chip resistor packages through via structure modification

Abstract We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests.

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