A VLSI implementation structure for wavelet decomposition filter

In recent years, the wavelet transform has found its wide use in various fields with the fast tower decomposition algorithm as a powerful tool. The DWT just takes the same position in the wavelet analysis as the FFT in the Fourier analysis and so its fast hardware implementation is very crucial to the wavelet application. In this paper, a high-speed implementation structure is derived by introducing the parallel systolic structure into the design of the wavelet decomposition filter. The structure has the advantages of higher computing speed and higher data flowing rate and lower power consumption with the presence of systolic and parallel techniques.