Multiple-gate SOI MOSFETs: device design guidelines

This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.

[1]  D. Hisamoto,et al.  A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET , 1989, International Technical Digest on Electron Devices Meeting.

[2]  Hiroshi Hiroshima,et al.  Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs , 2000 .

[3]  X. Baie,et al.  A silicon-on-insulator quantum wire , 1996 .

[4]  S. Cristoloveanu,et al.  Reduced floating body effects in narrow channel SOI MOSFETs , 2002, IEEE Electron Device Letters.

[5]  P. Ko,et al.  The behavior of narrow-width SOI MOSFETs with MESA isolation , 2000 .

[6]  James D. Plummer,et al.  A simple model for threshold voltage of surrounding-gate MOSFET's , 1998 .

[7]  J. Denton,et al.  Fully depleted dual-gated thin-film SOI P-MOSFETs fabricated in SOI islands with an isolated buried polysilicon backgate , 1996, IEEE Electron Device Letters.

[8]  H.-S.P. Wong,et al.  Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[9]  Sorin Cristoloveanu,et al.  Ultimately thin SOI MOSFETs: special characteristics and mechanisms , 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

[10]  Bogdan Majkusiak,et al.  Semiconductor thickness effects in the double-gate SOI MOSFET , 1998 .

[11]  Ghavam G. Shahidi,et al.  SOI Technology Outlook for Sub-0.25 μm CMOS, Challenges and Opportunities , 1993, ESSDERC '93: 23rd European solid State Device Research Conference.

[12]  L. T. Su,et al.  Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's , 1994, IEEE Electron Device Letters.

[13]  T. Ernst,et al.  Buried oxide fringing capacitance: a new physical model and its implication on SOI device scaling and architecture , 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

[14]  Frederic Allibert,et al.  From SOI materials to innovative devices , 2001 .

[15]  J. Kavalieros,et al.  A 50 nm depleted-substrate CMOS transistor (DST) , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[16]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[17]  D. Hisamoto.  FD/DG-SOI MOSFET-a viable approach to overcoming the device scaling limit , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[18]  Tiao-Yuan Huang,et al.  Reduced reverse narrow channel effect in thin SOI nMOSFETs , 2000 .

[19]  Sorin Cristoloveanu,et al.  Narrow-channel effects in LOCOS-isolated SOI MOSFETs with variable thickness , 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

[20]  L. Akers,et al.  The inverse-narrow-width effect , 1986, IEEE Electron Device Letters.

[21]  J. Colinge,et al.  Silicon-on-insulator 'gate-all-around device' , 1990, International Technical Digest on Electron Devices.

[22]  G. Baccarani,et al.  A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects , 1999 .

[23]  T. Hiramoto,et al.  Impact of quantum mechanical effects on design of nano-scale narrow channel n- and p-type MOSFETs , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[24]  50-nm channel nMOSFET/SIMOX with an ultrathin 2- or 6-nm thick silicon layer and their significant features of operations , 1997, IEEE Electron Device Letters.

[25]  S. Samavedam,et al.  Metal gates for advanced sub-80-nm SOI CMOS technology , 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).

[26]  D. Frank,et al.  Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[27]  Jong-Tea Park,et al.  Pi-Gate SOI MOSFET , 2001, IEEE Electron Device Letters.

[28]  Kwang Il Kim,et al.  A 0.25-/spl mu/m, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor , 1999 .

[29]  B. Majkusiak.  Quantum-mechanical effects in SOI devices , 2001 .